- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8152 > N74F573DB,118 (NXP Semiconductors)IC DTYPE LATCH OCTAL 20SSOP PDF資料下載
參數(shù)資料
| 型號： | N74F573DB,118 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DTYPE LATCH OCTAL 20SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | 74F |
| 邏輯類型： | D 型透明鎖存器 |
| 電路： | 8:8 |
| 輸出類型： | 三態(tài) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 獨(dú)立電路： | 1 |
| 延遲時間 - 傳輸： | 3.5ns |
| 輸出電流高，低： | 3mA，24mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 935198670118 N74F573DB-T N74F573DB-T-ND |
Philips Semiconductors
Product specification
74F573/74F574
Latch/flip-flop
74F573 Octal Transparent Latch (3-State)
74F574 Octal D Flip-Flop (3-State)
2
1989 Oct 16
853-0083 97897
FEATURES
74F573 is broadside pinout version of 74F373
74F574 is broadside pinout version of 74F374
Inputs and Outputs on opposite side of package allow easy
interface to Microprocessors
Useful as an Input or Output port for Microprocessors
3-State Outputs for Bus interfacing
Common Output Enable
74F563 and 74F564 are inverting version of 74F573 and 74F574
respectively
3-State Outputs glitch free during power-up and power-down
These are High-Speed replacements for N8TS805 and N8TS806
DESCRIPTION
The 74F573 is an octal transparent latch coupled to eight 3-State
output buffers. The two sections of the device are controlled
independently by Enable (E) and Output Enable (OE) control gates.
The 74F573 is functionally identical to the 74F373 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocessors.
The data on the D inputs is transferred to the latch outputs when the
Enable (E) input is High. The latch remains transparent to the data
input while E is High and stores the data that is present one setup
time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE) controls all eight 3-State buffers
independent to the latch operation. When OE is Low, the latched or
transparent data appears at the outputs. When OE is High, the
outputs are in high impedance “off” state, which means they will
neither drive nor load the bus.
The 74F574 is functionally identical to the 74F374 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocesors.
It is an 8-bit, edge triggered register coupled to eight 3-State output
buffers. The two sections of the device are controlled independently
by the clock (CP) and Output Enable (OE) control gates.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE) controls all eight 3-State buffers
independently of the latch operation. When OE is Low, the latched
or transparent data appears at the outputs. When OE is High, the
outputs are in high impedance “off” state, which means they will
neither drive nor load the bus.
TYPE
TYPICAL
PROPAGATION DELAY
TYPICAL SUPPLY
CURRENT
(TOTAL)
74F573
5.0ns
35mA
TYPE
TYPICAL fMAX
TYPICAL SUPPLY
CURRENT
(TOTAL)
74F574
180MHz
50mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
PKG DWG #
20-Pin Plastic DIP
N74F573N, N74F574N
SOT146-1
20-Pin Plastic SOL
N74F573D, N74F574D
SOT163-1
20-Pin Plastic SSOP
N74F573DB
SOT339-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D0 - D7
Data inputs
1.0/1.0
20
A/0.6mA
E (74F573)
Latch Enable input (active falling edge)
1.0/1.0
20
A/0.6mA
OE
Output Enable input (active Low)
1.0/1.0
20
A/0.6mA
CP (74F574)
Clock Pulse input (active rising edge)
1.0/1.0
20
A/0.6mA
Q0 - Q7
3-State outputs
150/40
3.0mA/24mA
NOTE: One (1.0) FAST Unit Load is defined as: 20
A in the High state and 0.6mA in the Low state.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY74FCT2244CTSOCE4 | IC BUFF/DVR TRI-ST 8BIT 20SOICW |
| OSTOP214200 | CONN TERM BLK HDR 21POS 3.81MM |
| N74F573D,623 | IC DTYPE LATCH OCTAL 20SOIC |
| OSTTT054180 | TERM BLOCK PLUG 3.81MM 5POS |
| OSTTT052180 | TERM BLOCK PLUG 3.5MM 5POS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| N74F573DB-T | 功能描述:閉鎖 OCTAL D-TYPE LATCH RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| N74F573D-T | 功能描述:閉鎖 OCTAL D-TYPE LATCH RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| N74F573N | 功能描述:閉鎖 OCTAL D-TYPE LATCH RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| N74F573N,602 | 功能描述:閉鎖 OCTAL D-TYPE LATCH RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| N74F573N-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit D-Type Latch |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。