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參數(shù)資料
| 型號(hào)： | N04L163WC2AB-85I |
| 元件分類： | SRAM |
| 英文描述： | 256K X 16 STANDARD SRAM, 85 ns, PBGA48 |
| 封裝： | BGA-48 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大小： | 186K |
| 代理商： | N04L163WC2AB-85I |
(DOC# 14-02-017 REV H ECN# 01-1268)
6
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
N04L163WC2A
AMI Semiconductor, Inc.
Timing Test Conditions
Item
Input Pulse Level
0.1VCC to 0.9 VCC
Input Rise and Fall Time
5ns
Input and Output Timing Reference Levels
0.5 VCC
Output Load
CL = 30pF
Operating Temperature
-40 to +85 oC
Timing
Item
Symbol
-70
Units
2.3 - 2.65 V
2.7 - 3.6 V
Min.
Max.
Min.
Max.
Read Cycle Time
tRC
85
70
ns
Address Access Time
tAA
85
70
ns
Chip Enable to Valid Output
tCO
85
70
ns
Output Enable to Valid Output
tOE
30
25
ns
Byte Select to Valid Output
tLB, tUB
85
70
ns
Chip Enable to Low-Z output
tLZ
10
ns
Output Enable to Low-Z Output
tOLZ
55
ns
Byte Select to Low-Z Output
tLBZ, tUBZ
10
ns
Chip Disable to High-Z Output
tHZ
0
20
0
20
ns
Output Disable to High-Z Output
tOHZ
0
20
0
20
ns
Byte Select Disable to High-Z Output
tLBHZ, tUBHZ
0
20
0
20
ns
Output Hold from Address Change
tOH
10
ns
Write Cycle Time
tWC
85
70
ns
Chip Enable to End of Write
tCW
50
ns
Address Valid to End of Write
tAW
50
ns
Byte Select to End of Write
tLBW, tUBW
50
ns
Write Pulse Width
tWP
40
ns
Address Setup Time
tAS
00
ns
Write Recovery Time
tWR
00
ns
Write to High-Z Output
tWHZ
20
ns
Data to Write Time Overlap
tDW
40
ns
Data Hold from Write Time
tDH
00
ns
End Write to Low-Z Output
tOW
55
ns
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