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參數(shù)資料
| 型號： | MXL1116 |
| 英文描述： | Ultra-Fast.Precision TTL Comparators |
| 中文描述： | 超F(xiàn)ast.Precision的TTL比較 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 41K |
| 代理商： | MXL1116 |
M
Ultra-Fast Prec ision T T L Comparators
_________________________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS – MXL1116
(V+ = 5V, V– = –5V, V
OUT
(Q) = 1.4V, V
LE
= 0V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Specifications for V
OS
, I
B
, CMRR and A
V
are valid for single-supply operation, V+ = 5V, V– = 0V.)
PARAMETER
MIN
CONDITIONS
UNITS
Power-Supply Rejection Ratio
TYP
1.0
Positive Supply: 4.6V
≤
V+
≤
5.4V
Negative Supply: –7V
≤
V–
≤
–2V
dB
Small-Signal Voltage Gain
MAX
±3
3.5
1V
≤
V
OUT
≤
2V, T
A
= +25°C
I
SOURCE
= 1mA
I
SOURCE
= 10mA
I
SINK
= 4mA
I
SINK
= 10mA, T
A
= +25°C
V/V
Output High Voltage
V
60
80
2.4
Positive Supply Current
Negative Supply Current
Latch Pin High Input Voltage
75
100
mA
mA
V
1400
2.7
3000
3.4
3.0
0.3
0.4
Input Offset Voltage
(Note 1)
Input Offset-Voltage Drift
Input Offset Current
(Note 1)
R
S
≤
100
mV
0.5
μV/°C
27
5
2
38
7
μA
Latch Pin Low Input Voltage
V
10
20
Input Bias Current, Sourcing
(Note 2)
5
Latch Input Current
V
LE
= 0V
V
IN
= 100mV,
OD = 5mV
μA
Propagation Delay
(Note 3)
ns
Differential Propagation Delay
(Note 3)
V
IN
= 100mV, OD = 5mV, T
A
= +25°C
ns
Latch Setup Time (Note 4)
Latch Hold Time (Note 4)
ns
ns
2.0
0.8
–20
12
–500
16
18
10
14
16
3
2
2
Single 5V supply
–5V
≤
V
CM
≤
2.5V
0V
≤
V
CM
≤
2.5V, V
S
= +5V, 0V
V–
0
(V+ – 2.5)
2.5
75
65
90
90
SYMBOL
PSRR
A
V
V
OH
Input Voltage Range
V
Common-Mode Rejection Ratio
I+
I–
V
IH
dB
V
OS
V
OS
/
T
I
OS
V
IL
I
IL
t
PD
t
PD
t
SU
t
H
V
CM
CMRR
μA
I
B
V
IN
= 100mV,
OD = 20mV
Output Low Voltage
V
0.5
V
OL
Note 1:
Input offset voltage is defined as the average of the two input offset voltages, measured by forcing first one output, then the
other to 1.4V. Input offset current is defined in the same way.
Note 2:
Input bias current (I
B
) is defined as the average of the two input currents.
Note 3:
t
PD
and
t
PD
cannot be measured in automatic handling equipment with low values of overdrive. Correlation tests have
shown that t
PD
and
t
PD
limits shown can be guaranteed by design, if additional DC tests are performed to guarantee that
all internal bias conditions are correct. For low overdrive conditions, V
OS
is added to overdrive.
Note 4:
Input latch setup time, t
SU
, is the interval in which the input signal must be stable prior to asserting the latch signal. The hold
time, t
H
, is the interval after the latch is asserted in which the input signal must be stable.
T
A
= +25°C
T
A
= +25°C
T
A
= +25°C
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