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參數(shù)資料
| 型號： | MXA-256-2 |
| 英文描述： | Optoelectronic |
| 中文描述： | 光電 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 1530K |
| 代理商： | MXA-256-2 |
www.perkinelmer.com/opto
Pin-Out Table
MXA-256-1, 2
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
FUNCTION
PIN #
FUNCTION
NC
Cap 5pF Dis
TEC +
CAP 2PF Dis
NC
Thermistor
Thermistor
NC
Ev Clock
NC
Ev EOS
NC
Ev Video 1
Ev Video 2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
Int/Reset
TEC
NC
Cap 10pF Dis
Vdd
Vss
Vref
Odd Clock
NC
Odd EOS
NC
Odd Video 1
Odd Video 2
Cap 5pF Dis/ Cap 2pF Dis/ Cap 10pF Dis:
These 3 TTL inputs control the size of the integration
capacitance well. When the pin is at high state (default) that particular capacitor is added to the
integration well size. When all the three pins are in the low state, the well size is set to the default base
value of 0.4pF well size. This provides a variable size of integration well - 0.4, 2.4, 5.4, 7.4, 10.4, 12.4,
15.4, and 17.4pF
TEC +/- :
These are the thermoelectric cooler pins
Thermistor:
Thermistor resistance at 25°C: 5 K
Ev Clock/Odd Clock:
These are the timing and readout clock inputs. These are TTL compatible
inputs. Both the Ev Clock and Odd Clock can be fed with the same clock, so the odd and even pixels are
synchronized
Int/Reset:
This is a TTL compatible input used to control the integration and reset of the integration
well. Integration occurs when this signal is high and reset occurs when this signal is low. Readout occurs
during the reset time. Care should be taken to provide enough time to readout the data. The Int/Reset
signal does not have to be synchronous with the Ev Clock/Odd Clock.
01-001:121201/9
Definitions
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