參數(shù)資料
型號(hào)： MX98742
廠商： MACRONIX INTERNATIONAL CO LTD
元件分類： 微控制器/微處理器
英文描述： Low-Cost 100Mbps Fast Ethernet Bridge Controller(低成本100Mbps快速以太網(wǎng)橋控制器)
中文描述： 2 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝： PLASTIC, QFP-160
文件頁數(shù)： 1/42頁
文件大小： 211K
代理商： MX98742
P/N : PM0403
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1.0
FEATURES
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2-port MAC bridge supports both Fast Ethernet and Ethernet/Fast Ethernet bridging
Minimum 16K byte, maximum 256K byte buffer memory
Selectable TX/FX/T4 symbol-level repeater, MII interfaces, and 10BASE serial port
T4 symbol mode includes the implementation of all PCS layers functions (8B/6T encode/decode, DE Balance
encode/decode, error detection, ....etc.)
512-bit hash filtering
Broadcast and Multicast packet filtering and inverse filtering
Optional fast forwarding modes minimizes latency
Optional dynamic auto buffer sizing
JAM-based flow control ensures lossless buffering
External Destination and Source Address filtering support
Display of buffer boundary and flow-control JAM packet counts
LED indication of flow-control JAM events
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2.0
GENERAL DESCRIPTION
The Fast Ethernet Bridge Controller (FEBC) is a low-cost solution to link fast Ethernet repeaters together so that the
distance between nodes can be expanded far beyond the 200m collision domain limitation. Each network segment
connected through the bridge is in a separate collision domain, and the FEBC's function is to exchange all the good
packets between two collision domain segments. A 512-bit hash filter is implemented to further reduce the traffic
between segments if it is desired. A 10/100 bridge function is also supported.
The FEBC has two forwarding modes: (1) store-and forward : a complete packet is buffered before it is to be forwarded.
Packets with CRC errors and other anomalies are discarded. (2) 64-byte forward : a packet is forwarded after the first
64 bytes are buffered. The number of bridges that can be put in one network is constrained largely by the buffer memory
and performance consideration. Multiple FEBCs are totally invisible to the upper layer protocol.
The FEBC supports direct TX PHY interface and 25MHz-MII on both side. Port A of the FEBC also supports TX and
T4 repeater ports at the symbobl level and port B of the FEBC also supports the 7-wire serial 10 MHz interface. The
FEBC supports buffer memory from minimum 16 Kbytes to 256 Kbytes. The memory is partitioned into two sections
with section A as the receive buffer for port A and section B for port B. The size of each section is equal if both sides
are operating at 100 Mbps speed; the minimum size of each section is 8 Kbytes. In the auto-sizing mode, the FEBC
will change the buffer size according to traffic pattern in each segment.
REV. 1.4, AUG. 5, 1997
MX98742
FEBC
100 BASE FAST ETHERNET
BRIDGE CONTROLLER
PRELIMINARY
相關(guān)PDF資料
PDF描述
MX98743 100 Base Fast Ethernet Management Chip(100 Base快速以太網(wǎng)管理芯片)
MX98745 100 BASE-TX/FX Repeater Controller(100 BASE-TX/FX 中繼器控制器)
MX98746 100 Base-TX/FX 5-Port ClassII Repeater Controller(100 Base-TX/FX 5端口 ClassII中繼器控制器)
MX98747 10/100M 8 Port Dual Speed HUB(10/100M 8端口雙速集線器)
MX98748 Highly Intergated 10/100M Dual Speed Hub With Extra 4 Port Switch Built-In(高度集成，內(nèi)置額外4端口開關(guān)的10/100M 雙速集線器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MX98743 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller
MX98745 制造商:未知廠家 制造商全稱:未知廠家 功能描述:100 BASE-TX/FX REPEATER CONTROLLER
MX98746 制造商:未知廠家 制造商全稱:未知廠家 功能描述:100 Base-TX/FX 5-Port Class II Repeater Controller
MX98747 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100M 8PORT DUAL SPEED HUB CONTROLLER
MX98748 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Highly Intergated 10/100M Dual Speed Hub With Extra 4 Port Switch Built-In
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