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參數(shù)資料
| 型號： | MX98216EC |
| 廠商： | MACRONIX INTERNATIONAL CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 17/37頁 |
| 文件大?。?/td> | 269K |
| 代理商： | MX98216EC |
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MX98216EC
P/N:PM0781
REV. 0.2, Apr, 18, 2001
24
FUNCTIONAL DESCRIPTION
Clocks
MX98216EC requires a unique 50MHz clock signal for both RMII and system requirement at CLK input pin.
Also, the
switch generates an 8.3MHz output clock to CPU and the processor feedback the same clock rate back to the switch.
The 2.5MHz clock applies on MDC/MDIO interface and 390KHz refers EEPROM interface.
Reset
When power on, a hard reset is initiated by an active low pulse on RESET# pin.
The initialization process loads all
ports configurable parameters, resets internal state machines to idle, initializes embedded memory and address table.
At the completion of the reset sequence, all ports are presented for packet transmission and reception.
RMII Interface
Reduced Media Independent Interface (RMII) comprises a low pin count intended for use between Ethernet PHYs and
switch ASICs.
The management interface (MDC/MDIO) is assumed to be identical to that defined in IEEE 802.3u.
The RMII specification has been optimized for using in high port density interconnect devices which require
independent treatment of the data paths.
The primary motivator is a switch ASIC which requires independent data
streams between the MAC and PHY.
CLK
CLK is a continuous clock that provides the timing reference for CRSDV_0-15, RXD_0-15[1:0], TXEN_0-15, and
TXD_0-15[1:0].
The switch choose to provide CLK as an input for system and RMII use and each PHY device shall
have an input corresponding to this clock but may use a single clock input for multiple PHYs implemented on a single
IC.
Carrier Sense/Receive Data Valid
CRSDV_0-15 shall be asserted by the PHY when the receive medium is non-idle.
The specifics of the definition of
idle for 10BASE-T and 100BASE-X are contained in IEEE 802.3 and IEEE 802.3u.
CRSDV0-15 is asserted
asynchronously on detection of carrier due to the criteria relevant to the operating mode.
That is, in 10BASE-T mode,
when squelch is passed or, in 100BASE-X mode, when 2 non-contiguous zeroes in 10 bits are detected carrier is said
to be detected.
If the PHY has additional bits to be presented on RXD_0-15[1:0] following the initial deassertion of
CRSDV_0-15, then the PHY shall assert CRSDV_0-15 on cycles of CLK which present the second di-bit of each
nibble and deassert CRSDV_0-15 on cycles of CLK which present the first di-bit of a nibble.
Receive Data
RXD_0-15[1:0] shall transition synchronously to CLK. For each clock period in which CRSDV_0-15 is asserted,
RXD_0-15[1:0] transfers two bits of recovered data from the PHY.
In some cases, for example before data recovery
or during error conditions, a pre-determined value for RXD_0-15[1:0] is transferred instead of recovered data.
RXD_0-15[1:0] shall be “ 00” to indicate idle when CRSDV_0-15 is deasserted.
Values other than “ 00” on RXD_0-
15[1:0] while recovered from CRSDV_0-15 is de-asserted shall be ignored by the MAC.
Upon assertion of
CRSDV_0-15, the PHY shall ensure that RXD_0-15[1:0] is equal to ” 00” until proper receive decoding takes place.
Transmit Enable
TXEN_0-15 indicates that the MAC is presenting di-bits on TXD_0-15[1:0] for transmission. TXEN_0-15 shall be
asserted synchronously with the first nibble of the preamble and shall remain asserted while all di-bits to be
transmitted are presented.
TXEN_0-15 shall be negated prior to the first CLK rising edge following the final di-bit of a
frame.
TXEN_0-15 shall transition synchronously with respect to CLK.
Transmit Data
TXD_0-15[1:0] shall transition synchronously with respect to CLK.
When TXEN_0-15 is asserted, TXD[1:0] are
accepted for transmission by the PHY.
TXD_0-15[1:0] shall be “ 00” to indicate idle when TXEN_0-15 is deasserted.
Values other than “ 00” on TXD_0-15[1:0] while TXEN_0-15 is deasserted shall be ignored by the PHY.
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