參數(shù)資料
型號: MX839P
廠商: Electronic Theatre Controls, Inc.
英文描述: Digitally Controlled Analog I/O Processor
中文描述: 數(shù)字控制的模擬I / O處理器
文件頁數(shù): 8/20頁
文件大?。?/td> 165K
代理商: MX839P
Digitally Controlled Analog I/O Processor
8
MX839 PRELIMINARY INFORMATION
1998 MX
x
COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480164.002
All trademarks and service marks are held by their respective companies.
4.5.2
Write Only Register (8-Bit and 16-Bit)
HEX
ADDRESS/
COMMAN
D
$01
REGISTER
NAME
BIT 7
(D7)
BIT 6
(D6)
BIT 5
(D5)
BIT 4
(D4)
BIT 3
(D3)
BIT 2
(D2)
BIT 1
(D1)
BIT 0
(D0)
RESET
CLOCK
CONTROL
VARIABLE
ATTENUATOR (1)
VARIABLE
ATTENUATOR (2)
DAC
CONTROL
DAC1 DATA
(1)
*See Note 1
(2)
DAC2 DATA
(1)
*See Note 1
(2)
DAC3 DATA
(1)
*See Note 1
(2)
A/D
CONTROL
N/A
N/A
N/A
N/A
N/A
N/A
N/A
DIVIDER
BIT 1
N/A
$D0
0
0
0
0
0
BIT 2
MOD1
BIT 2
MOD2
BIT 2
DAC2
ENABLE
BIT 0
MOD1
ENABLE
MOD2
ENABLE
NBIT
DAC3
$D2
0
0
BIT 4
BIT 3
BIT 1
BIT 0
0
0
BIT 4
BIT 3
DAC1
ENABLE
BIT 1
DAC3
ENABLE
BIT 0
NBIT
DAC1
NBIT
DAC2
$D3
0
0
$D4
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
0
0
0
BIT 9
BIT 8
$D5
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
0
0
0
BIT 9
BIT 8
$D6
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
0
0
0
BIT 9
A/DIN4
ACTIVE
BIT 8
A/DIN1
ACTIVE
A/DIN2
ACTIVE
A/DIN3
ACTIVE
$D7
0
1
READ
MAGNITUDE COMPARATOR UPPER LEVEL
BIT 5
BIT 4
MAGNITUDE COMPARATOR LOWER LEVEL
BIT 5
BIT 4
MAGNITUDE COMPARATOR UPPER LEVEL
BIT 5
BIT 4
MAGNITUDE COMPARATOR LOWER LEVEL
BIT 5
BIT 4
MAGNITUDE COMPARATOR UPPER LEVEL
BIT 5
BIT 4
MAGNITUDE COMPARATOR LOWER LEVEL
BIT 5
BIT 4
MAGNITUDE COMPARATOR UPPER LEVEL
BIT 5
BIT 4
MAGNITUDE COMPARATOR LOWER LEVEL
BIT 5
BIT 4
0
MAG COMP ONE
LEVELS (1)
MAG COMP ONE
LEVELS (2)
MAG COMP TWO
LEVELS (1)
MAG COMP TWO
LEVELS (2)
MAG COMP THREE
LEVELS (1)
MAG COMP THREE
LEVELS (2)
MAG COMP FOUR
LEVELS (1)
MAG COMP FOUR
LEVELS (2)
$D8
BIT 7
BIT 6
BIT 3
BIT 2
BIT 1
BIT 0
BIT 7
BIT 6
BIT 3
BIT 2
BIT 1
BIT 0
$D9
BIT 7
BIT 6
BIT 3
BIT 2
BIT 1
BIT 0
BIT 7
BIT 6
BIT 3
BIT 2
BIT 1
BIT 0
$DA
BIT 7
BIT 6
BIT 3
BIT 2
BIT 1
BIT 0
BIT 7
BIT 6
BIT 3
BIT 2
BIT 1
BIT 0
$DB
BIT 7
BIT 6
BIT 3
BIT 2
BIT 1
BIT 0
BIT 7
BIT 6
BIT 3
BIT 2
BIT 1
BIT 0
Table 2: Write Only Register (8-Bit and 16-Bit)
Note
1. A second byte is expected by the 'C-BUS' interface only when the 'NBIT DACn bit of the 'DAC Control Register' is
set high. Otherwise, the data transfer is a single byte (Bit 7 to Bit 0).
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