參數(shù)資料
型號(hào)： MX7534KP+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 16/16頁(yè)
文件大?。?/td> 0K
描述： IC DAC 14BIT MPU COMP 20-PLCC
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 49
設(shè)置時(shí)間： 800ns
位數(shù)： 14
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 20-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 28-PLCC（11.51x11.51）
包裝： 管件
輸出數(shù)目和類型： 1 電流，單極；1 電流，雙極
采樣率（每秒）： *
MX7534/MX7535
Microprocessor-Compatible,
14-Bit DACs
_______________________________________________________________________________________
9
Gain Adjustment
(Figures 6a and 6b)
1) Load DAC register with all 1s.
2) Trim potentiometer R3 so that VOUT = -
(
16383)VIN
16384
Low-Leakage Configuration
Leakage current in the DAC flowing into the IOUT line
can cause gain, linearity, and offset errors. Leakage is
worse at high temperatures.
Negatively bias VSS for a high-temperature, low-leakage
configuration.
Dynamic Considerations
In static or DC applications, the output amplifier’s AC
characteristics are not critical. In higher-speed applica-
tions, where either the reference input is an AC signal
or the DAC output must quickly settle to a new pro-
grammed value, the output op amp’s AC parameters
must be considered.
Another error source in dynamic applications is the par-
asitic signal coupling from the REF terminal to IOUT.
This is normally a function of board layout and lead-to-
lead package capacitance. Signals can also be inject-
ed into the DAC outputs when the digital inputs are
switched. This digital feedthrough depends on circuit-
board layout and on-chip capacitive coupling. Minimize
layout-induced feedthrough with guard traces between
digital inputs, REF, and DAC outputs.
R1
100
R2, 33
R6
20k
R7
20k
R5 10k
R8, 5k,10%
INPUT
DATA
ANALOG
GROUND
A0
A1
A2
A1
7–14
WR
CS
16
620
5
4
3
2
19
1
C1
33pF
VIN
VDD
VSS
MX7534
REF
RFB
IOUT
AGNDS
AGNDF
DGND
D7–D0
15
18
17
+
VO
Figure 5a. Bipolar Operation
R1
20
R2 10
R6
20k
R7
20k
R5
10k
R8, 5k,10%
INPUT
DATA
ANALOG
GROUND
LDAC
A1
A2
CSMSB
8–21
WR
CSLSB
23
7
27
6
5
4
3
2
26
1
C1
33pF
VIN
VDD
VSS
MX7535
REFF REFS
RFB
IOUT
AGNDS
AGNDF
DGND
D13–D0
22
25
24
+
VO
Figure 5b. Bipolar Operation
CSMSB CSLSB LDAC
WR
FUNCTION
0
1
0
Load MS Input Register
1
0
1
0
Load LS Input Register
0010
Load LS and MS Input
Registers
110
X
Load DAC Register
from Input Register
0000
All registers are
transparent.
1
X
No operation
X
1
No operation
Table 3. MX7535 Logic States
Table 4. Offset Binary Bipolar Code Table
BINARY NUMBER IN
DAC REGISTER
Analog Output
(VOUT)
MSB
LSB
11
1111
10
0000
0001
10
0000
01
1111
00
0000
+VIN
(8191)
8192
+VIN
( 1 )
8192
0
-VIN
( 1 )
8192
-VIN
(8192) = -VIN
8192
Note:
X = Don’t Care.
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