參數(shù)資料
型號(hào): MX29LV640TXBI-90
廠商: MACRONIX INTERNATIONAL CO LTD
元件分類(lèi): DRAM
英文描述: 64M-BIT [8M x 8/4M x 16] SINGLE VOLTAGE 3V ONLY FLASH MEMORY
中文描述: 4M X 16 FLASH 3V PROM, 90 ns, PBGA63
封裝: 11 X 12 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, PLASTIC, MO-210, CSP-63
文件頁(yè)數(shù): 24/70頁(yè)
文件大小: 1188K
代理商: MX29LV640TXBI-90
24
P/N:PM0920
REV. 1.2, NOV. 05, 2003
MX29LV640T/B
AUTOMATIC CHIP/SECTOR ERASE COM-
MAND
The device does not require the system to preprogram
prior to erase. The Automatic Erase algorithm automati-
cally pre-program and verifies the entire memory for an
all zero data pattern prior to electrical erase. The system
is not required to provide any controls or timings during
these operations. Table 2 shows the address and data
requirements for the chip erase command sequence.
Any commands written to the chip during the Automatic
Erase algorithm are ignored. Note that a hardware reset
during the chip erase operation immediately terminates
the operation. The Chip Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
The system can determine the status of the erase op-
eration by using Q7, Q6, Q2, or RY/BY. See "Write Op-
eration Status" for information on these status bits. When
the Automatic Erase algorithm is complete, the device
Pins
Manufacture code
Device code for MX29LV640T
A0
VIL
VIH
A1
VIL
VIL
Q7
1
1
Q6
1
1
Q5
0
0
Q4
0
0
Q3
0
1
Q2
0
0
Q1
1
0
Q0
0
1
Code(Hex)
C2H
22C9H (word)
XXC9H (byte)
22CBH (word)
XXCBH (byte)
Device code for MX29LV640B
VIH
VIL
1
1
0
0
1
0
1
1
TABLE 3. SILICON ID CODE
SETUP AUTOMATIC CHIP/SECTOR ERASE
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cycles
are then followed by the chip erase command 10H, or
the sector erase command 30H.
returns to reading array data and addresses are no longer
latched.
Figure 3 illustrates the algorithm for the erase operation.
See the Erase/Program Operations tables in "AC Char-
acteristics" for parameters, and to Figure 16 for timing
diagrams.
sector boundaries. A bit cannot be programmed from a
"0" back to a "1". Attempting to do so may halt the
operation and set Q5 to "1" ,” or cause the Data Polling
algorithm to indicate the operation was successful.
However, a succeeding read will show that the data is
still "0". Only erase operations can convert a "0" to a
"1".
The MX29LV640T/B contains a Silicon-ID-Read opera-
tion to supplement traditional PROM programming meth-
odology. The operation is initiated by writing the read
silicon ID command sequence into the command regis-
ter. Following the command write, a read cycle with
A1=VIL,A0=VIL retrieves the manufacturer code of C2H.
A read cycle with A1=VIL, A0=VIH returns the device
code of 22C9H/22CBH for MX29LV640T/B.
相關(guān)PDF資料
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MX29LV640TXCC-12 64M-BIT [8M x 8/4M x 16] SINGLE VOLTAGE 3V ONLY FLASH MEMORY
MX29LV640TXCC-90 64M-BIT [8M x 8/4M x 16] SINGLE VOLTAGE 3V ONLY FLASH MEMORY
MX29LV640TXCI-12 64M-BIT [8M x 8/4M x 16] SINGLE VOLTAGE 3V ONLY FLASH MEMORY
MX29LV640TXCI-90 64M-BIT [8M x 8/4M x 16] SINGLE VOLTAGE 3V ONLY FLASH MEMORY
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