參數(shù)資料
型號(hào)： MX29LV320TXEC-12G
廠商： MACRONIX INTERNATIONAL CO LTD
元件分類： DRAM
英文描述： 32 BIT 4M X 8 / 2M X 16 ] SINGLE VOLTAGE 3V ONLY FLASH MEMORY
中文描述： 2M X 16 FLASH 3V PROM, 120 ns, PBGA48
封裝： 8 X 9 MM, 1.30 MM HEIGTH, 0.80 MM PITCH, PLASTIC, MO-219, CSP-48
文件頁(yè)數(shù)： 12/63頁(yè)
文件大?。?/td> 949K
代理商： MX29LV320TXEC-12G
12
P/N:PM0742
REV. 1.4, JUL. 04, 2003
MX29LV320T/B
OUTPUT DISABLE
With the OE input at a logic high level (VIH), output from
the devices are disabled. This will cause the output pins
to be in a high impedance state.
RESET OPERATION
The RESET pin provides a hardware method of resetting
the device to reading array data. When the RESET pin is
driven low for at least a period of tRP, the device
immediately terminates any operation in progress,
tristates all output pins, and ignores all read/write
commands for the duration of the RESET pulse. The
device also resets the internal state machine to reading
array data. The operation that was interrupted should be
reinitiated once the device is ready to accept another
command sequence, to ensure data integrity
Current is reduced for the duration of the RESET pulse.
When RESET is held at VSS
±
0.3V, the device draws
CMOS standby current (ICC4). If RESET is held at VIL
but not within VSS
±
0.3V, the standby current will be
greater.
The RESET pin may be tied to system reset circuitry. A
system reset would that also reset the Flash memory,
enabling the system to read the boot-up firm-ware from
the Flash memory.
If RESET is asserted during a program or erase
operation, the RY/BY pin remains a "0" (busy) until the
internal reset operation is complete, which requires a time
of tREADY (during Embedded Algorithms). The system
can thus monitor RY/BY to determine whether the reset
operation is complete. If RESET is asserted when a
program or erase operation is not executing (RY/BY pin
is "1"), the reset operation is completed within a time of
tREADY (not during Embedded Algorithms). The system
can read data tRH after the RESET pin returns to VIH.
Refer to the AC Characteristics tables for RESET
parameters and to Figure 14 for the timing diagram.
SECTOR GROUP PROTECT OPERATION
The MX29LV320T/B features hardware sector group pro-
tection. This feature will disable both program and erase
operations for these sector group protected. To activate
this mode, the programming equipment must force V
ID
on address pin A9 and control pin OE, (suggest V
=
12V) A6 = VIL and CE = VIL.(see Table 2) Programming
of the protection circuitry begins on the falling edge of
the WE pulse and is terminated on the rising edge. Please
refer to sector group protect algorithm and waveform.
MX29LV320T/B also provides another method which re-
quires V
on the RESET only. This method can be imple-
mented either in-system or via programming equipment.
This method uses standard microprocessor bus cycle
timing.
To verify programming of the protection circuitry, the pro-
gramming equipment must force V
on address pin A9 (
with CE and OE at VIL and WE at VIH). When A1=1, it
will produce a logical "1" code at device output Q0 for a
protected sector. Otherwise the device will produce 00H
for the unprotected sector. In this mode, the addresses,
except for A1, are don't care. Address locations with
A1= VIL are reserved to read manufacturer and device
codes.(Read Silicon ID)
It is also possible to determine if the group is protected
in the system by writing a Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
a logical "1" at Q0 for the protected sector.
CHIP UNPROTECT OPERATION
The MX29LV320T/B also features the chip unprotect
mode, so that all sectors are unprotected after chip
unprotect is completed to incorporate any changes in
the code. It is recommended to protect all sectors before
activating chip unprotect mode.
To activate this mode, the programming equipment must
force V
on control pin OE and address pin A9. The CE
pins must be set at VIL. Pins A6 must be set to VIH.(see
Table 2) Refer to chip unprotect algorithm and wave-
form for the chip unprotect algorithm. The unprotection
mechanism begins on the falling edge of the WE pulse
and is terminated on the rising edge.
MX29LV320T/B also provides another method which re-
quires V
on the RESET only. This method can be imple-
mented either in-system or via programming equipment.
This method uses standard microprocessor bus cycle
timing.
It is also possible to determine if the chip is unprotected
in the system by writing the Read Silicon ID command.
相關(guān)PDF資料
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