參數(shù)資料
型號(hào)： MX29LV004TQC-70
廠商： MACRONIX INTERNATIONAL CO LTD
元件分類： DRAM
英文描述： 4M-BIT [512K x 8] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY
中文描述： 512K X 8 FLASH 3V PROM, 70 ns, PQCC32
封裝： PLASTIC, MS-016, LCC-32
文件頁數(shù)： 19/54頁
文件大?。?/td> 724K
代理商： MX29LV004TQC-70
19
P/N:PM0732
MX29LV004T/B
REV. 1.1, SEP. 19, 2001
Table 8. CAPACITANCE TA = 25
o
C, f = 1.0 MHz
SYMBOL
CIN1
CIN2
COUT
PARAMETER
Input Capacitance
Control Pin Capacitance
Output Capacitance
MIN.
TYP
MAX.
8
12
12
UNIT
pF
pF
pF
CONDITIONS
VIN = 0V
VIN = 0V
VOUT = 0V
NOTES:
1.VIL min. = -1.0V for pulse width is equal to or less than 50 ns.
VIL min. = -2.0V for pulse width is equal to or less than 20 ns.
2.VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns
If VIH is over the specified maximum value, read operation cannot be guaranteed.
3.Automatic sleep mode enable the low power mode when addresses remain stable for tACC +30ns.
READ OPERATION
Symbol
PARAMETER
MIN.
TYP
MAX.
UNIT
CONDITIONS
ILI
Input Leakage Current
±
1
uA
VIN = VSS to VCC
ILIT
A9 Input Leakage Current
35
uA
VCC=VCC max; A9=12.5V
ILO
Output Leakage Current
±
1
uA
VOUT = VSS to VCC, VCC=VCC max
ICC1
VCC Active Read Currect
7
12
mA
CE=VIL, OE=VIH
@5MHz
2
4
mA
@1MHz
ICC2
VCC Active write Currect
15
30
mA
CE=VIL, OE=VIH
ICC3
VCC Standby Currect
0.2
5
uA
CE; RESET=VCC
±
0.3V
(RESET pin for 40-TSOP)
ICC4
VCC Standby Currect
0.2
5
uA
RESET=VSS
±
0.3V
During Reset
(RESET pin for 40-TSOP)
ICC5
Automative sleep mode
0.2
5
uA
VIH=VCC
±
0.3V;VIL=VSS
±
0.3V
VIL
Input Low Voltage(Note 1)
-0.5
0.8
V
VIH
Input High Voltage
0.7xVCC
VCC+ 0.3
V
VID
Voltage for Automative
Select and Temporary
11.5
12.5
V
VCC=3.3V
Chip Unprotect
VOL
Output Low Voltage
0.45
V
IOL = 4.0mA, VCC= VCC min
VOH1
Output High Voltage(TTL)
0.85xVCC
IOH = -2mA, VCC=VCC min
VOH2
Output High Voltage
VCC-0.4
IOH = -100uA, VCC min
(CMOS)
VLKO
Low VCC Lock-out
2.3
2.5
V
Voltage
Table 9. DC CHARACTERISTICS TA = -40
o
C TO 85
o
C, VCC = 2.7V to 3.6V
(TA = 0
o
C TO 70
o
C, VCC = 3.3V
±
5% for MX29LV004T/B-55R)
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