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參數(shù)資料
| 型號(hào)： | MX29F200TTC-70 |
| 廠商： | MACRONIX INTERNATIONAL CO LTD |
| 元件分類： | DRAM |
| 英文描述： | Fully Differential I/O Audio Amplifier 8-SOIC -40 to 85 |
| 中文描述： | 128K X 16 FLASH 5V PROM, 70 ns, PDSO48 |
| 封裝： | 12 X 20 MM, PLASTIC, MO-142, TSOP1-48 |
| 文件頁數(shù)： | 13/46頁 |
| 文件大小： | 720K |
| 代理商： | MX29F200TTC-70 |
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13
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
MX29F200T/B
Exceeded Timing Limits
Q5 will indicate if the program or erase time has exceeded
the specified limits(internal pulse count). Under these
conditions Q5 will produce a "1". This time-out condition
which indicates that the program or erase cycle was not
successfully completed. Data Polling and Toggle Bit are
the only operating functions of the device under this
condition.
If this time-out condition occurs during sector erase
operation, it specifies that a particular sector is bad and
it may not be reused. However, other sectors are still
functional and may be used for the program or erase
operation. The device must be reset to use other
sectors. Write the Reset command sequence to the
device, and then execute program or erase command
sequence. This allows the system to continue to use the
other active sectors in the device.
If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or
combination of sectors are bad.
If this time-out condition occurs during the byte
programming operation, it specifies that the entire
sector containing that byte is bad and this sector maynot
be reused, (other sectors are still functional and can be
reused).
The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this
case the device locks out and never completes the
Automatic Algorithm operation. Hence, the system
never reads a valid data on Q7 bit and Q6 never stops
toggling. Once the Device has exceeded timing limits,
the Q5 bit will indicate a "1". Please note that this is not
a device failure condition since the device was incorrectly
used.
Sector Erase Timer
After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is still
open. If Q3 is high ("1") the internally controlled erase
cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the
command has been accepted, the system software
should check the status of Q3 prior to and following each
subsequent sector erase command. If Q3 were high on
the second status check, the command may not have
been accepted.
DATA PROTECTION
The MX29F200T/B is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power
transition. During power up the device automatically
resets the state machine in the Read mode. In addition,
with its control register architecture, alteration of the
memory contents only occurs after successful completion
of specific command sequences. The device also
incorporates several features to prevent inadvertent
write cycles resulting from VCC power-up and power-
down transition or system noise.
TEMPORARY SECTOR UNPROTECT
This feature allows temporary unprotection of previously
protected sector to change data in-system. The Tempo-
rary Sector Unprotect mode is activated by setting the
RESET pin to VID(11.5V-12.5V). During this mode,
formerly protected sectors can be programmed or erased
as un-protected sector. Once VID is remove from the
RESET pin,all the previously protected sectors are
protected again.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns(typical) on CE or WE will
not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE
= VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Q3
Q5
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| MX29F200TTC-90 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:2M-BIT [256Kx8/128Kx16] CMOS FLASH MEMORY |
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| MX29F200TTI-70 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:2M-BIT [256Kx8/128Kx16] CMOS FLASH MEMORY |
| MX29F200TTI-90 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:2M-BIT [256Kx8/128Kx16] CMOS FLASH MEMORY |
| MX29F4000 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:4M-BIT [512KX8] CMOS EQUAL SECTOR FLASH MEMORY |
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