
5
P/N:PM0900
MX28F640C3T/B
REV. 0.6, AUG. 20, 2003
Table 1. Pin Description
Symbol
A0-A21
Type
input
Description and Function
Address inputs for memory address. Data pin float to high-impedance when the chip is
deselected or outputs are disable. Addresses are internally latched during a write or
erase cycle.
Data inputs/outputs: Inputs array data on the second CE and WE cycle during a pro-
gram command. Data is internally latched. Outputs array and configuration data. The
data pin float to tri-state when the chip is de-selected.
Activates the device's control logic, input buffers, and sense amplifiers. CE high de-
selects the memory device and reduce power consumption to standby level. CE is
active low.
Reset Deep Power Down: when RESET=VIL, the device is in reset/deep power down
mode, which drives the outputs to High Z, resets the WSM and minimizes current level.
When RESET=VIH, the device is normal operation. When RESET transition the device
defaults to the read array mode.
Write Enable: to control write to CUI and array sector. WR=VIL becomes active. The
data and address is latched WE on the rising edge of the second WE pulse.
Program/Erase Power Supply:(1.65V~3.6V)
Lower VPP<VPPLK, to protect any contents against Program and Erase Command.
Set VPP=VCC for in-system Read, Program and Erase Operation.
Output enable: gates the device's outputs during a real cycle.
Write protect: when WP is VIL, the boot sectors cannot be written or erased. When WP
is VIH, locked boot sectors cannot be written or erase. WP is not affected parameter
and main sectors.
Device power supply: (2.7V~3.6V).
I/O Power Supply: supplies for input/output buffers.
[2.7V~3.6V] This input should be tied directly to VCC.
Ground voltage: all the GND pin shall not be connected.
Q0-Q15
input/output
CE
input
RESET
input
WE
input
VPP
input/supply
OE
WP
input
input
VCC
VCCQ
supply
input
GND
supply