參數(shù)資料
型號(hào)： MX28F640C3BTTI-90
廠商： MACRONIX INTERNATIONAL CO LTD
元件分類： DRAM
英文描述： 64M-BIT [4M x16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY
中文描述： 4M X 16 FLASH 3V PROM, 90 ns, PDSO48
封裝： 12 X 20 MM, MO-142, TSOP1-48
文件頁(yè)數(shù)： 4/41頁(yè)
文件大?。?/td> 307K
代理商： MX28F640C3BTTI-90
4
P/N:PM1084
MX28F640C3BT/B
REV. 0.0, MAR. 17, 2004
PIN CONFIGURATIONS
48 TSOP (Standard Type) (12mm x 20mm)
A15
A14
A13
A12
A11
A10
A9
A8
A21
A20
WE#
RESET#
VPP
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
VCCQ
GND
Q15
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
GND
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX28F640C3T/B
Table 1. Pin Description
Symbol
A0-A21
Type
input
Description and Function
Address inputs for memory address. Data pin float to high-impedance when the chip is
deselected or outputs are disable. Addresses are internally latched during a write or erase
cycle.
Data inputs/outputs: Inputs array data on the second CE# and WE# cycle during a program
command. Data is internally latched. Outputs array and configuration data. The data pin float
to tri-state when the chip is de-selected.
Activates the device's control logic, input buffers, and sense amplifiers. CE# high de-se-
lects the memory device and reduce power consumption to standby level. CE# is active low.
Reset Deep Power Down: when RESET#=VIL, the device is in reset/deep power down
mode, which drives the outputs to High Z, resets the WSM and minimizes current level.
When RESET#=VIH, the device is normal operation. When RESET# transition the device
defaults to the read array mode.
Write Enable: to control write to CUI and array sector. WR#=VIL becomes active. The data
and address is latched WE# on the rising edge of the second WE# pulse.
Program/Erase Power Supply:(1.65V~3.6V or 11.4V~12.6V)
Lower VPP<VPPLK, to protect any contents against Program and Erase Command.
Set VPP=VCC for in-system Read, Program and Erase Operation.
Raise VPP to 12V
±
5% for faster program and erase in a production environment.
Output enable: gates the device's outputs during a real cycle.
Write protect: when WP# is VIL, the boot sectors cannot be written or erased. When WP# is
VIH, locked boot sectors cannot be written or erase. WP is not affected parameter and main
sectors.
Device power supply: (2.7V~3.6V).
I/O Power Supply: supplies for input/output buffers.
[2.7V~3.6V] This input should be tied directly to VCC.
Ground voltage: all the GND pin shall not be connected.
Q0-Q15
input/output
CE#
input
RESET#
input
WE#
input
VPP
input/supply
OE#
WP#
input
input
VCC
VCCQ
supply
input
GND
supply
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