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    參數(shù)資料
    型號: MX27C1024QC-15
    廠商: MACRONIX INTERNATIONAL CO LTD
    元件分類: DRAM
    英文描述: 1M-BIT [128K x 8/64K x 16] CMOS EPROM
    中文描述: 64K X 16 OTPROM, 150 ns, PQCC44
    封裝: PLASTIC, MS-016, LCC-44
    文件頁數(shù): 5/20頁
    文件大?。?/td> 965K
    代理商: MX27C1024QC-15
    5
    REV. 4.4 , AUG. 20, 2001
    P/N: PM0156
    MX27C1100/27C1024
    arrays, a 4.7 uF bulk electrolytic capacitor should be
    used between VCC and GND for each eight devices.
    The location of the capacitor should be close to where
    the power supply is connected to the array.
    BYTE-WIDE MODE
    With BYTE/VPP at GND
    ±
    0.2V, outputs Q8-15 are tri-
    stated. If Q15/A-1 = VIH, outputs Q0-7 present data bits
    Q8-15. If Q15/A-1 = VIL, outputs Q0-7 present data bits
    Q0-7.
    STANDBY MODE
    The MX27C1100/1024 has a CMOS standby mode
    which reduces the maximum VCC current to 100 uA. It
    is placed in CMOS standby when CE is at VCC
    ±
    0.3 V.
    The MX27C1100/1024 also has a TTL-standby mode
    which reduces the maximum VCC current to 1.5 mA. It
    is placed in TTL-standby when CE is at VIH. When in
    standby mode, the outputs are in a high-impedance
    state, independent of the OE input.
    TWO-LINE OUTPUT CONTROL FUNCTION
    To accommodate multiple memory connections, a two-
    line control function is provided to allow for:
    1. Low memory power dissipation,
    2. Assurance that output bus contention will not
    occur.
    It is recommended that CE be decoded and used as the
    primary device-selecting function, while OE be made a
    common connection to all devices in the array and
    connected to the READ line from the system control bus.
    This assures that all deselected memory devices are in
    their low-power standby mode and that the output pins
    are only active when data is desired from a particular
    memory device.
    SYSTEM CONSIDERATIONS
    During the switch between active and standby
    conditions, transient current peaks are produced on the
    rising and falling edges of Chip Enable. The magnitude
    of these transient current peaks is dependent on the
    output capacitance loading of the device. At a minimum,
    a 0.1 uF ceramic capacitor (high frequency, low inherent
    inductance) should be used on each device between
    Vcc and GND to minimize transient effects. In addition,
    to overcome the voltage drop caused by the inductive
    effects of the printed circuit board traces on EPROM
    相關(guān)PDF資料
    PDF描述
    MX27C1024QC-55 1M-BIT [128K x 8/64K x 16] CMOS EPROM
    MX27C1024QC-70 1M-BIT [128K x 8/64K x 16] CMOS EPROM
    MX27C1024QC-85 1M-BIT [128K x 8/64K x 16] CMOS EPROM
    MX27C1024TC-10 1M-BIT [128K x 8/64K x 16] CMOS EPROM
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    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    MX27C1024QC-55 制造商:MCNIX 制造商全稱:Macronix International 功能描述:1M-BIT [128K x 8/64K x 16] CMOS EPROM
    MX27C1024QC-70 制造商:MCNIX 制造商全稱:Macronix International 功能描述:1M-BIT [128K x 8/64K x 16] CMOS EPROM
    MX27C1024QC-85 制造商:MCNIX 制造商全稱:Macronix International 功能描述:1M-BIT [128K x 8/64K x 16] CMOS EPROM
    MX27C1024TC-10 制造商:MCNIX 制造商全稱:Macronix International 功能描述:1M-BIT [128K x 8/64K x 16] CMOS EPROM
    MX27C1024TC-12 制造商:MCNIX 制造商全稱:Macronix International 功能描述:1M-BIT [128K x 8/64K x 16] CMOS EPROM