參數(shù)資料
型號(hào): MX23C4096PC-12
廠商: Electronic Theatre Controls, Inc.
英文描述: 4M-BIT [256K x 16] CMOS MASK ROM
中文描述: 4分位[256K × 16]的CMOS掩膜ROM
文件頁(yè)數(shù): 1/6頁(yè)
文件大?。?/td> 53K
代理商: MX23C4096PC-12
1
P/N:PM0257
REV. 1.3, OCT. 08, 1996
PIN CONFIGURATION
40PDIP
44 PLCC
FEATURES
256K x 16 organization (JEDEC pin out)
Single +5V power supply
Fast access time: 100/120/150/200ns
Totally static operation
Completely TTl compatible
PIN DESCRIPTION
Symbol
A0~A17
Q0~Q15
CE/CE
OE/OE
VCC
VSS
Pin Function
Address Inputs
Data Outputs
Chip Enable Input
Output Enable Input
Power Supply Pin (+5V)
Ground Pin
MX23C4096
4M-BIT [256K x 16] CMOS MASK ROM
Operating current: 60mA
Standby current: 100uA
Package
- 40 pin DIP (600 mil)
- 44 pin PLCC
GENERAL DESCRIPTION
The MX23C4096 is a 5V only, 4M-bit, Read Only
Memory. It is organized as 512Kx16 bit. MX23C4096
has a static standby mode, and has an access time of
100/120/150/200ns. It is designed to be compatible with
all microprocessors and similar applications in which
high performance, large bit storage and simple interfac-
ing are important design considerations.
MX23C4096 offers automatic power-down, with power-
down controlled by the chip enable (CE/CE) input. When
CE/CE is not selected, the device automatically powers
down and remains in a low-power standby mode as long
as CE/CE stays in the unselected mode.
The OE/OE inputs as well as CE/CE input may be pro-
grammed either active High or Low.
M
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NC
CE/CE
Q15
Q14
Q13
Q12
Q11
Q10
Q9
Q8
VSS
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
OE/OE
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
A17
A16
A15
A14
A13
A12
A11
A10
A9
VSS
A8
A7
A6
A5
A4
A3
A2
A1
A0
MX23C4096
Q12
Q11
Q10
Q9
Q8
VSS
NC
Q7
Q6
Q5
Q4
A13
A12
A11
A10
A9
VSS
NC
A8
A7
A6
A5
Q
Q
Q
C
N
N
V
A
A
A
A
Q
Q
Q
Q
O
N
A
A
A
A
A
6
44
40
39
34
29
28
7
12
17
18
23
1
BLOCK DIAGRAM
CONTROL
LOGIC
OUTPUT
BUFFERS
Q0~Q15
CE/CE
OE/OE
A0~A17
ADDRESS
INPUTS
Y-DECODER
X-DECODER
Y-DECODER
4M BIT
ROM
ARRAY
VCC
VSS
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
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INDEX
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