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      參數(shù)資料
      型號: MVTX2604AG
      廠商: ZARLINK SEMICONDUCTOR INC
      元件分類: 網(wǎng)絡(luò)接口
      英文描述: Managed 24-Port 10/100 Mb + 2 Port 1 Gb Ethernet Switch
      中文描述: DATACOM, LAN SWITCHING CIRCUIT, PBGA553
      封裝: 37.50 X 37.50 MM, 2.33 MM HEIGHT, MS-034, HSBGA-553
      文件頁數(shù): 15/173頁
      文件大?。?/td> 2097K
      代理商: MVTX2604AG
      MVTX2604
      Data Sheet
      17
      Zarlink Semiconductor Inc.
      2.0 System Configuration (Stand-alone and Stacking)
      2.1 Management and Configuration
      Two modes are supported in the MVTX2604: managed and unmanaged. In managed mode, the MVTX2604 uses
      an 8 or 16 bit CPU interface very similar to the Industry Standard Architecture (ISA) specification. In unmanaged
      mode, the MVTX2604 has no CPU but can be configured by EEPROM using an I
      2
      C interface at bootup, or via a
      synchronous serial interface otherwise.
      2.2 Managed Mode
      In managed mode, the MVTX2604 uses an 8 or 16 bit CPU interface very similar to the ISA bus. The MVTX2604
      CPU interface provides for easy and effective management of the switching system. Figure 2 provides an overview
      of the CPU interface.
      Figure 2 - Overview of the MVTX2604 CPU Interface
      2.3 Register Configuration, Frame Transmission, and Frame Reception
      2.3.1 Register Configuration
      The MVTX2604 has many programmable parameters, covering such functions as QoS weights, VLAN control and
      port mirroring setup. In managed mode, the CPU interface provides an easy way of configuring these parameters.
      The parameters are contained in 8-bit configuration registers. The MVTX2604 allows indirect access to these
      registers, as follows:
      If operating in 8 bits-interface mode, two “index” registers (addresses 000 and 001) need to be written to
      indicate the desired 8-bit register address. In 16-bit mode, only one register (address 000) needs to be
      written for the desired 16-bit register address.
      INDEX REG 1
      (Addr = 001)
      INDEX REG 0
      (Addr = 000)
      CONFIG
      DATA REG
      (Addr = 010)
      CONTROL
      BLOCK REG
      SYNOCHRONOUS
      SERIAL
      INTERFACE
      FRAME DATA REG
      (Addr = 011)
      INTERNAL
      CONFIGURE
      REGISTERS
      CPU
      FRAME
      RECEIVE
      FIFO
      CONTROL
      COMMAND
      FRAME
      RECEIVE
      FIFO
      CPU
      FRAME
      TRANSMIT
      FIFO
      CONTROL
      COMMAND
      FRAME
      TRANSMIT
      FIFO
      1 AND 2
      8 bit internal
      data bus
      8/16 bit internal
      data bus
      8/16 bit internal
      data bus
      16 bit internal
      address bus
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