
MVTX2602
Data Sheet
16
Zarlink Semiconductor Inc.
In addition, there are nine types of Control frames generated by the MVTX2602 and sent to the CPU:
Interrupt CPU when statistics counter rolls over
Response to memory read request from CPU
Learn MAC address
Delete MAC address
Delete IP Multicast address
New VLAN port
Age out VLAN port
Response to search MAC address request from CPU
Response to search IP Multicast address request from CPU
The format of the Control Frame is described in the processor interface application note.
2.4 Unmanaged Mode
In unmanaged mode, the MVTX2602 can be configured by EEPROM (24C02 or compatible) via an I2C interface at
boot time, or via a synchronous serial interface during operation.
2.5 I2C Interface
The I2C interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries the
control signals that facilitate the transfer of information from EEPROM to the switch. Data transfer is 8-bit serial and
bidirectional, at 50 Kbps. Data transfer is performed between master and slave IC using a request /
acknowledgment style of protocol. The master IC generates the timing signals and terminates data transfer.
Figure 3 depicts the data transfer format.
Figure 3 - Data Transfer Format for I2C Interface
2.5.1 Start Condition
Generated by the master (in our case, the MVTX2602). The bus is considered to be busy after the Start condition is
generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA line.
Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High
period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the I2C bus is
free, both lines are High.
2.5.2 Address
The first byte after the Start condition determines which slave the master will select. The slave in our case is the
EEPROM. The first seven bits of the first data byte make up the slave address.
2.5.3 Data Direction
The eighth bit in the first byte after the Start condition determines the direction (R/W) of the message. A master
transmitter sets this bit to W; a master receiver sets this bit to R.
START
SLAVE ADDRESS
R/W
ACK
DATA 1
(8 bits)
AC
K
DATA 2
ACK
DATA M
ACK
STOP