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XMEGA A [MANUAL]
8077I–AVR–11/2012
Figure 7-4.
32.768kHz crystal oscillator connection.
Two capacitors, C1 and C2, may be added to match the required load capacitance for the connected crystal. For details
on recommended TOSC characteristics and capacitor load, refer to device datasheets.
7.5
System Clock Selection and Prescalers
All the calibrated internal oscillators, the external clock sources (XOSC), and the PLL output can be used as the system
clock source. The system clock source is selectable from software, and can be changed during normal operation. Built-in
hardware protection prevents unsafe clock switching. It is not possible to select a non-stable or disabled oscillator as the
clock source, or to disable the oscillator currently used as the system clock source. Each oscillator option has a status
flag that can be read from software to check that the oscillator is ready.
The system clock is fed into a prescaler block that can divide the clock signal by a factor from 1 to 2048 before it is routed
to the CPU and peripherals. The prescaler settings can be changed from software during normal operation. The first
stage, prescaler A, can divide by a factor of from 1 to 512. Then, prescalers B and C can be individually configured to
either pass the clock through or combine divide it by a factor from 1 to 4. The prescaler guarantees that derived clocks
are always in phase, and that no glitches or intermediate frequencies occur when changing the prescaler setting. The
prescaler settings are updated in accordance with the rising edge of the slowest clock.
Figure 7-5.
System clock selection and prescalers.
Prescaler A divides the system clock, and the resulting clock is clk
PER4. Prescalers B and C can be enabled to divide the
clock speed further to enable peripheral modules to run at twice or four times the CPU clock frequency. If Prescalers B
and C are not used, all the clocks will run at the same frequency as the output from Prescaler A.
The system clock selection and prescaler registers are protected by the configuration change protection mechanism,
employing a timed write procedure for changing the system clock and prescaler settings. For details, refer to
7.6
PLL with 1x-31x Multiplication Factor
The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a user-
selectable multiplication factor of from 1 to 31. The output frequency, fOUT, is given by the input frequency, fIN, multiplied
by the multiplication factor, PLL_FAC.
C1
C2
TOSC2
TOSC1
GND
Prescaler A
1, 2, 4, ... , 512
Prescaler B
1, 2, 4
Prescaler C
1, 2
Internal 2MHz Osc.
Internal 32.768kHz Osc.
Internal 32MHz Osc.
External Oscillator or Clock.
ClkCPU
Clock Selection
ClkPER
ClkSYS
ClkPER2
ClkPER4
Internal PLL.