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參數(shù)資料
| 型號(hào)： | MV1442 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | HDB3 Encoder/Decoder/Clock Regenerator |
| 中文描述： | 采用HDB3編碼器/解碼器/時(shí)鐘再生器 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 726K |
| 代理商： | MV1442 |
4
MV1442
1 CLOCK PERIOD
RXD1
RXD2
DECODER
CLOCK
NOTE
The LOSS OF INPUT output is delayed by one clock period with respect to the incoming HDB3 waveform
LOSS OF
INPUT
1
2
3
4
5
6
7
8
9
10
11
Figure 6 - Loss of input waveforms
1
2
3
4
5
6
7
8
9
Pin
Signal name
Description
NRZ DATA IN
ENCODER CLOCK
LOSS OF INPUT
NRZ DATA OUT
DECODER CLOCK
RESET AIS
AIS
MODE
GND
Input pin for data to be encoded into pseudo-ternary HDB3 form. This data is clocked into
the Encoder block by the falling edge of ENCODER CLOCK.
Clock input for the encoding of data on pin 1.
Output from the loss of input circuit This output goes high one clock period after the
detection of eleven consecutive zeros on the decoder inputs. Any logic ‘1’ at the input
(RXD1 or RXD2=0) resets this count after a single clock period delay.
NRZ data output obtained from the decoding of the pseudo-ternary inputs to the Decoder
block.
Clock input to the Decoder block for decoding data on RXD1 and RXD2 or TXD1 and TXD2
in loop test mode. In internal clock regeneration mode, this pin is used to output the
regenerated clock to external circuitry. In external clock regeneration, mode this pin is
used to input the externally regenerated clock signal direct to the Decoder block.
Reset input to the decoded zero counter A logic ‘0’ on this input resets a decoded zero
counter. It will also reset the AIS output to ‘0’ provided 3 or more zeros have been decoded
in the preceding RESET AIS = 1 period or set AIS to 1 if less than 3 zeros have been
decoded in the preceding RESET AIS = 1 period This may be used to indicate loss of
timeslot zero. A logic ‘1’ on this pin enables the decoded zero counter.
Output from AIS circuit (see description for pin 6).
Input pin for selection of clock regeneration mode. A logic high on this input selects internal
crystal controlled clock regeneration while a logic low selects external clock regeneration.
Digital ground 0V.
Table 1 - Pin descriptions
Contd…
DECODER
CLOCK
NRZ DATA OUT
RESET AIS
AIS
Figure 7 - AIS and RESET AIS waveforms
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MV1442DPAS | HDB3 Encoder/Decoder/Clock Regenerator |
| MV1442IG | HDB3 Encoder/Decoder/Clock Regenerator |
| MV1442MPES | HDB3 Encoder/Decoder/Clock Regenerator |
| MV1471CGDGAS | Encoder/Decoder |
| MV1471CGDPAS | Encoder/Decoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MV1442/IG/DPAS | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
| MV1442/IG/MPES | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
| MV1442DG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Encoder/Decoder |
| MV1442DP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Encoder/Decoder |
| MV1442DPAS | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:HDB3 Encoder/Decoder/Clock Regenerator |
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