參數(shù)資料
型號(hào): MUN5333DW1T1
廠商: ON SEMICONDUCTOR
元件分類: 小信號(hào)晶體管
英文描述: Dual Bias Resistor Transistors(雙偏置電阻晶體管)
中文描述: 100 mA, 50 V, 2 CHANNEL, NPN AND PNP, Si, SMALL SIGNAL TRANSISTOR
封裝: CASE 419B-02, 6 PIN
文件頁(yè)數(shù): 1/35頁(yè)
文件大?。?/td> 373K
代理商: MUN5333DW1T1
Semiconductor Components Industries, LLC, 2005
December, 2005
Rev. 11
1
Publication Order Number:
MUN5311DW1T1/D
MUN5311DW1T1 Series
Preferred Devices
Dual Bias Resistor
Transistors
NPN and PNP Silicon Surface Mount
Transistors with Monolithic Bias
Resistor Network
The BRT (Bias Resistor Transistor) contains a single transistor with
a monolithic bias network consisting of two resistors; a series base
resistor and a base
emitter resistor. These digital transistors are
designed to replace a single device and its external resistor bias
network. The BRT eliminates these individual components by
integrating them into a single device. In the MUN5311DW1T1 series,
two complementary BRT devices are housed in the SOT
363 package
which is ideal for low power surface mount applications where board
space is at a premium.
Features
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
Available in 8 mm, 7 inch/3000 Unit Tape and Reel
Pb
Free Packages are Available
MAXIMUM RATINGS
(T
A
= 25
°
C unless otherwise noted, common for Q
1
and Q
2
,
minus sign for Q
1
(PNP) omitted)
Rating
Symbol
Value
Unit
Collector-Base Voltage
V
CBO
50
Vdc
Collector-Emitter Voltage
V
CEO
50
Vdc
Collector Current
I
C
100
mAdc
THERMAL CHARACTERISTICS
Characteristic
(One Junction Heated)
Total Device Dissipation
T
A
= 25
°
C
Derate above 25
°
C
Symbol
P
D
Max
Unit
mW
187 (Note 1)
256 (Note 2)
1.5 (Note 1)
2.0 (Note 2)
670 (Note 1)
490 (Note 2)
mW/
°
C
Thermal Resistance
Junction-to-Ambient
Characteristic
(Both Junctions Heated)
Total Device Dissipation
T
A
= 25
°
C
Derate above 25
°
C
R
JA
°
C/W
Symbol
P
D
Max
Unit
mW
250 (Note 1)
385 (Note 2)
2.0 (Note 1)
3.0 (Note 2)
493 (Note 1)
325 (Note 2)
188 (Note 1)
208 (Note 2)
55 to +150
mW/
°
C
Thermal Resistance
Junction-to-Ambient
Thermal Resistance
Junction-to-Lead
Junction and Storage Temperature
1. FR
4 @ Minimum Pad
2. FR
4 @ 1.0 x 1.0 inch Pad
R
JA
°
C/W
R
JL
°
C/W
T
J
, T
stg
°
C
SOT
363
CASE 419B
STYLE 1
MARKING DIAGRAM
6
Preferred
devices are recommended choices for future use
and best overall value.
ORDERING AND DEVICE MARKING
INFORMATION
See detailed ordering, shipping, and specific marking
information in the table on page 2 of this data sheet.
Q
1
R
1
R
2
R
2
R
1
Q
2
(1)
(2)
(3)
(4)
(5)
(6)
http://onsemi.com
1
6
xx
M
1
xx
M
= Device Code
= Date Code*
= Pb
Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
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