參數(shù)資料
型號： MUAC4K64-50TDC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP100
封裝： TQFP-100
文件頁數(shù)： 13/32頁
文件大?。?/td> 504K
代理商： MUAC4K64-50TDC
MUAC Routing CoProcessor (RCP) Family
Control State Descriptions
20
Rev. 4
Control State:
Indirect Write at Address;
Increment Address Register
Mnemonic:
WRs[AR]+{MRnnn}
Binary Op-Code: XXX nnn 100 110
/W: LOW
/AV: HIGH
PA:AA: aaa
Scope: AS
Description: Writes data from the DQ31-0 bus to bits
31-0 (DSC LOW) or 63-32 (DSC HIGH) of the location
defined by the contents of the Address register. The
validity of the location is set by the state of the /VB input,
/VB = LOW: Valid, /VB = HIGH: Empty. The write is
masked by bits 31-0 (DSC LOW) or 63-32 (DSC HIGH)
of the contents of Mask Register nnn. When nnn=000 no
mask is used; when masking is selected, only bits in the
addressed location that correspond to LOW values in the
selected mask register are updated. The contents of the
Address register are incremented.
Control State:
Indirect Read at Address;
Increment Address Register
Mnemonic:
RDs[AR]+
Binary Op-Code: XXX XXX 100 110
/W: HIGH
/AV: HIGH
PA:AA: aaa
Scope: S
Description: Reads data from bits 31-0 (DSC LOW) or
63-32 (DSC HIGH) of the location defined by the contents
of the Address register to the DQ31-0 bus. This control
state provides indirect random access memory reads.
During the Read cycle, the /VB line carries the Validity Bit
value of the addressed location. The contents of the
Address register are incremented.
Control State:
Indirect Write at Address;
Decrement Address Register
Mnemonic:
WRs[AR]-{MRnnn}
Binary Op-Code: XXX nnn 100 111
/W: LOW
/AV: HIGH
PA:AA: aaa
Scope: AS
Description: Writes data from bits 31–0 (DSC LOW) or
63-32 (DSC HIGH) of the DQ31–0 bus to the location
defined by the contents of the Address register. The
validity of the location is set by the state of the /VB input,
/VB = LOW: Valid, /VB = HIGH: Empty. The write is
masked by bits 31–0 (DSC LOW) or 63-32 (DSC HIGH)
of the contents of Mask Register nnn. When nnn=000 no
mask is used; when masking is selected, only bits in the
addressed location that correspond to LOW values in the
selected mask register are updated. The contents of the
Address register are decremented.
Control State:
Indirect Read at Address;
Decrement Address Register
Mnemonic:
RDs[AR]-
Binary Op-Code: XXX XXX 100 111
/W: HIGH
/AV: HIGH
PA:AA: aaa
Scope: S
Description: Reads data from bits 31–0 (DSC LOW) or
63-32 (DSC HIGH) of the location defined by the contents
of the Address register to the DQ31–0 bus. This control
state provides indirect random access memory reads.
During the Read cycle, the /VB line carries the Validity Bit
value of the addressed location. The contents of the
Address register are decremented.
Control State:
Write to Highest-Priority
Matching Location
Mnemonic:
WRs[HPM]{MRnnn}
Binary Op-Code: XXX nnn 000 010
/W: LOW
/AV: HIGH
PA:AA: HPMA
Scope: HPD
Description: Writes data from the DQ31-0 bus to bits
31-0 (DSC LOW) or 63-32 (DSC HIGH) of the
highest-priority matching location in the Memory array.
The validity of the location is set by the state of the /VB
input, /VB=LOW: Valid, /VB=HIGH: Empty. The write is
masked by bits 31–0 (DSC LOW) or 63-32 (DSC HIGH)
of the contents of Mask Register nnn. When nnn=000 no
mask is used; when masking is selected, only bits in the
addressed location that correspond to LOW values in the
selected mask register are updated.
Control State:
Read Highest-Priority
Matching Location
Mnemonic:
RDs[HPM]
Binary Op-Code: XXX XXX 000 010
/W: HIGH
/AV: HIGH
PA:AA: HPMA
Scope: HPD
Description: Reads data from bits 31–0 (DSC LOW) or
63-32 (DSC HIGH) the
location
defined by the
highest-priority matching location to the DQ31–0 bus. In
the event that the previous Comparison cycle resulted in a
mismatch,
the
DQ31–0
bus
will
remain
in
high-impedance.
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