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| 型號： | MU9C1902-35PC |
| 英文描述： | x9 Asynchronous FIFO |
| 中文描述： | X9熱賣異步FIFO |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 246K |
| 代理商： | MU9C1902-35PC |
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MU9C1480A/L Draft
Rev. 3.0 Draft
14
OPERATIONAL CHARACTERISTICS Continued
Figure 3: Read Cycle
Figure 4: Write Cycle
Figure 5: Cycle to Cycle Timing Example
The ripple delay of the flags when connected in a daisy
chain requires the extension of the /E HIGH time until the
logic in all devices has settled out. In a string of “n” devices,
the /E HIGH time should be greater than
tEHMFV + (n-2)
·
tMIVMFV
If the last device’s Match flag is required by external logic
or a state machine before the start of the next CAM cycle,
one additional tMIVMFV should be added to the
/E HIGH time along with the setup time and delays for the
external logic.
Locked Daisy Chain
In a locked daisy chain, the highest-priority device is the
one with /MI HIGH and /MF LOW. In Standard mode, only
this device will respond to command and data reads and
writes, until the daisy chain has been unlocked by taking
/EC HIGH. This allows reading the associated data field
from only the Highest-Priority Match location anywhere in
a string of devices, or the Match address from the Status
register of the device with the match. It also permits
updating the entry stored at the Highest-Priority Match
location. In Enhanced mode, devices are enabled to respond
to some command and data writes, as noted in Table 5b,
but not command and data reads.
/E
DQ15-0
/W
/CM
/EC
DATA OUT
/E
DQ15–0
/W
/CM
/EC
/E
DQ15–0
/W
/CM
COM PARAND W RITE
CYCLE
TA
STATUS READ
CYCLE
ASS OCIATED DATA
READ CYCLE
DATA
DATA
/MA AND /MM FL AGS UPDATED
/MA, /MM
DA
/EC
/M F
MATCH FLAG VALID
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| MU9C1902-35EC | x9 Asynchronous FIFO |
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| MU9C1902-25PC | x9 Asynchronous FIFO |
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| MU9C248012DC | 制造商:MUSIC 功能描述:* |
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