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| 型號： | MU9C1640-55DC |
| 英文描述： | Content Addressable Memory |
| 中文描述： | 內(nèi)容可尋址存儲器 |
| 文件頁數(shù)： | 22/28頁 |
| 文件大?。?/td> | 246K |
| 代理商： | MU9C1640-55DC |
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MU9C1480A/L Draft
Rev. 3.0 Draft
22
Table 10: Next Free Address Register Bit Assignments
Table 11: Status Register Bit Assignments
Table 9: Segment Control Register Bit Assignments
REGISTER BIT ASSIGNMENTS Continued
Set
Dest.
Seg.
Limits
= 0
No
Chng.
= 1
Set
Source
Seg.
Limits
= 0
No
Chng.
= 1
Load
Dest.
Seg.
Count
= 0
No
Chng.
= 1
Load
Src.
Seg.
Count
= 0
No
Chng.
= 1
Note:
D15, D10, D5, and D2 read back as 0s.
Destination
Count
Start
Limit
= 00–11
Destination
Count
End
Limit
= 00–11
Source
Count
Start
Limit
= 00–11
Source
Count
End
Limit
= 00–11
Destination
Seg.
Count
Value
= 00–11
Source
Seg.
Count
Value
= 00–11
15
14
13
12
11
10
SSL
9
8
7
6
5
4
3
2
1
0
SDL
DCSL
DCEL
SCSL
SCEL
LDC
DSCV
LSC
SSCV
15
14
13
12
11
10
9
8
7
Next Free Address, NF9–0
6
5
4
3
2
1
0
Note:
The Next Free Address register is read only, and is accessed by performing a Command Read
cycle immediately following a TCO NF instruction.
Page Address, PA5–PA0
9
Note:
The Status register is read only, and is accessed by performing Command Read cycles. On the first
cycle, bits 15–0 will be output, and if a second Command Read cycle is issued immediately after the
first Command Read cycle, bits 31–16 will be output.
15
Page Address, PA4–PA0
14
13
12
11
10
8
7
6
5
4
3
2
1
0
/FL
/MM
Skip
31
30
29
28
27
0
26
25
24
Page Address Bits, PA15-PA5
23
22
21
20
19
18
17
16
Match Address, AM9-AM0
/MA
Empty
Table 12: Persistent Source Register Bit Assignments
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Device ID = 141H
PS
Note:
The Persistent Source register is read only, and is accessed by performing a Command Read cycle
immediately following a TCO PS instruction.
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