參數(shù)資料
型號(hào)： MTV212A32
廠商： Electronic Theatre Controls, Inc.
英文描述： 8051 Embedded Monitor Controller Mask ROM Type
中文描述： 8051嵌入式控制器掩模ROM顯示器類型
文件頁(yè)數(shù)： 17/23頁(yè)
文件大小： 167K
代理商： MTV212A32
MYSON
TECHNOLOGY
MTV212A32
(Rev. 1.2)
Revision 1.2 - 17 - 2000/07/04
= 0
→
Current transfer is slave receive
→
The external IIC host respond NACK.
→
The slave block has detected a START, cleared when STOP detected.
SlvAlsb1,SlvAlsb0 : The 2 LSB which host send to Slave A block.
MAckIn = 1
→
Master IIC bus error, no ACK received from the slave IIC device.
= 0
→
ACK received from the slave IIC device.
Hifreq
= 1
→
MTV212A32 has detected a higher than 200Hz clock on the VSYNC pin.
Hbusy = 1
→
Host drives the HSCL pin to low.
SAckIn = 1
SLVS
= 1
INTFLG
(w) :
Interrupt flag. A interrupt event will set its individual flag, and, if the corresponding interrupt
enable bit is set, the 8051 INT1 source will be driven by a zero level. Software MUST clear
this register while serve the interrupt routine.
SlvBMI = 1
→
No action.
= 0
→
Clear SlvBMI flag.
SlvAMI = 1
→
No action.
= 0
→
Clear SlvAMI flag.
MbufI
= 1
→
No action.
= 0
→
Clear Master IIC bus interrupt flag (MbufI).
INTFLG
(r) :
Interrupt flag.
= 1
= 1
TXBI
RCBI
SlvBMI = 1
TXAI
RCAI
SlvAMI = 1
DbufI
MbufI
→
Indicates the TXBBUF need a new data byte, clear by writing TXBBUF.
→
Indicates the RCBBUF has received a new data byte, clear by reading RCBBUF.
→
Indicates the slave IIC address B match condition.
→
Indicates the TXABUF need a new data byte, clear by writing TXABUF.
→
Indicates the RCABUF has received a new data byte, clear by reading RCABUF.
→
Indicates the slave IIC address A match condition.
→
Indicates the DDC1 data buffer need a new data byte, clear by writing DBUF.
→
Indicates a byte is sent/received to/from the master IIC bus.
= 1
= 1
= 1
= 1
INTEN
(w) :
Interrupt enable.
ETXBI = 1
ERCBI = 1
ESlvBMI = 1
ETXAI = 1
ERCAI = 1
ESlvAMI = 1
EDbufI = 1
EMbufI = 1
→
Enable TXBBUF interrupt.
→
Enable RCBBUF interrupt.
→
Enable slave address B match interrupt.
→
Enable TXABUF interrupt.
→
Enable RCABUF interrupt.
→
Enable slave address A match interrupt.
→
Enable DDC1 data buffer interrupt.
→
Enable Master IIC bus interrupt.
Mbuf
(w) :
Master IIC data shift register, after START and before STOP condition, write this register will
resume MTV212A32's transmission to the IIC bus.
Mbuf
(r) :
Master IIC data shift register, after START and before STOP condition, read this register will
resume MTV212A32's receiving from the IIC bus.
RCABUF
(r) :
Slave IIC block A receive data buffer.
TXABUF
(w) :
Slave IIC block A transmit data buffer.
SLVAADR
(w) :Slave IIC block A's enable and address.
ENslvA = 1
→
Enable slave IIC block A.
= 0
→
Disable slave IIC block A.
bit6-0 :
Slave IIC address A to which the slave block should respond.
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