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參數(shù)資料
| 型號： | MTU8B57EN |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | EPROM-Based 8-Bit CMOS Microcontroller |
| 中文描述： | 存儲器為基礎(chǔ)的8位CMOS微控制器 |
| 文件頁數(shù)： | 4/23頁 |
| 文件大?。?/td> | 286K |
| 代理商： | MTU8B57EN |
Revision 1.2
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4 - 24 October 2000
MTU8B54E/55E/56E/57E
MYSON
TECHNOLOGY
3.1.1 INAR(Indirect Address Register) : R0
R0 is not a physically implemented register. It is used as an indirect addressing pointer. Any instruction
accessing this register can access data pointed by FSR(R4).
3.1.2 Timer0(8-bit real-time clock/timer) : R1
This register increases by an external signal edge applied to T0CKI pin, or by internal instruction cycle. It can
be read or written as any other register.
3.1.3 PC(Program Counter) : R2
This register increases itself every instruction cycle, except the following condition shown in Figure 1:
LCALL, LGOTO : from instruction word
RETIA : from STACK
3.1.4 STATUS(Status Register):
The content of R3 is listed in Table 1.
A10~A0
Stack1
Stack2
Stack3
Stack4
LCALL
RETIA
FIGURE 1. Program Counter
TABLE 1. STATUS Register
Bit
Symbol
Description
0
C
Carry/borrow bit
ADDWF SUBWF
= 1, a carry occurred = 1, a borrow did not occur
= 0, a carry did not occur = 0, a borrow occurred
Half carry/half borrow bit
ADDWF
= 1, a carry from the 4th low order bit of the result occurred
= 0, a carry from the 4th low order bit of the result did not occur
SUBWF
= 1, a borrow from the 4th low order bit of the result did not occur
= 0, a borrow from the 4th low order bit of the result occurred
Zero bit:
= 1, the result of a logic operation is zero
= 0, the result of a logic operation is not zero
Power down flag bit:
= 1, after power-up or by the CLRWDT instruction
= 0, by the SLEEP instruction
Time overflow flag bit:
= 1, after power-up or by the CLRWDT or SLEEP instruction
= 0, a WDT time-overflow occurred
Unused
1
DC
2
Z
3
PD
4
TO
5, 6, 7
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