參數(shù)資料
型號(hào)： MT9V011P11ST
廠商： Micron Technology, Inc.
英文描述： 1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
中文描述： 4英寸顯卡的CMOS有源像素的數(shù)字圖像傳感器
文件頁(yè)數(shù)： 27/33頁(yè)
文件大?。?/td> 537K
代理商： MT9V011P11ST
1/4-INCH VGA CMOS ACTIVE-PIXEL
DIGITAL IMAGE SENSOR
Preliminary
09005aef80c6407f
MT9V011_external_DS_2.fm - Rev. A 8/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
27
2004 Micron Technology, Inc.
Propagation Delays for PIXCLK and
Data Out Signals
The typical output delay, relative to the master
clock edge, is 7.5 ns. Note that the data outputs change
on the falling edge of the master clock, with the pixel
clock rising on the subsequent rising edge of the mas-
ter clock.
Propagation Delays for FRAME_VALID
and LINE_VALID Signals
The LINE_VALID and FRAME_VALID signals
change on the same falling master clock edge as the
data output. The LINE_VALID goes HIGH on the same
falling master clock edge as the output of the first valid
pixel's data and returns LOW on the same master clock
falling edge as the end of the output of the last valid
pixel's data.
As shown in the “Output Data Timing” on page 9,
FRAME_VALID goes HIGH 6 pixel clocks prior to the
time that the first LINE_VALID goes HIGH. It returns
LOW at a time corresponding to 6 pixel clocks after the
last LINE_VALID goes LOW.
Figure 19: Propagation Delays for PIXCLK and Data Out Signals
Figure 20: Propagation Delays for FRAME_VALID and LINE_VALID Signals
CLK_IN
PIXCLK
DOUT (7:0)
tPLH
D
, tPHL
D
tR
tF
CLK_IN
PIXCLK
tPLH
D
, tPLH
D
D
OUT
(9:0)
D
OUT
(9:0)
tOH
tPHL
P
tPLH
P
tR
tF
D
OUT
(9:0)
D
OUT
(9:0)
D
OUT
(9:0)
CLK_IN
FRAME_VALID
LINE_VALID
CLK_IN
FRAME_VALID
LINE_VALID
tPHL
FL
tPLH
FL
tF
tF
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