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參數(shù)資料
| 型號： | MT933TP1N |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 3.3V 10/100 Fast Ethernet Transceiver to MII |
| 中文描述： | 3.3 10/100快速以太網(wǎng)收發(fā)器，以信息產(chǎn)業(yè)部 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 360K |
| 代理商： | MT933TP1N |
13
MT933
reg 25 - ANEG status
Bit
Bit name
Description
Default
R/W
25.15:14
reserved
test mode only - do not set high
0
RO
25.13
Pol
1 indicates polarity reversal on RX inputs (10Base-T)
0
RO
25.12:8
PA
copy of PHY address pins
PA<4:0>
RO
25.7
aneg
complete
1 = aneg completed
0 = aneg did not complete (same as reg1.5)
0
RO
25.6
Duplex
ANEG result - duplex operation
0 = HDX, 1 = FDX
0
RO
25.5
speed
ANEG result - speed of operation
0 = 10M, 1 = 100M
0
RO
25.4
ability mtc
1 = abilities match between registers 4 & 5
0
RO
25.3:0
ANEG state
ANEG state machine current state
0
RO
reg 26 - Symbol error counter
Bit
Bit name
Description
Default
R/W
26.15:0
RX_ERR
counter
number of RX_ERR events since last read - Clears
either in change of speed or read of this reg.
0
RO
SC
reg 27 - False carrier event counter
Bit
Bit name
Description
Default
R/W
27.15
disconnect
the disconnect mechanism status
0
RO
LH
27.14:8
reserved
0
RO
27.7:0
false CRS
counter
number of False CRS events since last read.
Active only when DISCEN = 1
”
.
0
RO
SC
reg 28, 29, 30, 31 - Test registers
Bit
Bit name
Description
Default
R/W
15:0
reserved
test mode only
0000
res
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