參數(shù)資料
型號(hào): MT933CG
廠商: Zarlink Semiconductor Inc.
英文描述: 3.3V 10/100 Fast Ethernet Transceiver to MII
中文描述: 3.3 10/100快速以太網(wǎng)收發(fā)器,以信息產(chǎn)業(yè)部
文件頁數(shù): 13/20頁
文件大?。?/td> 360K
代理商: MT933CG
12
MT933
reg 21 - MII interrupt control register
Bit
Bit name
Clear Interrupt
Description
Write any data pattern to clear MINT
Default
0
R/W
WO
21.15:0
reg 22, 23 - Test registers
Bit
Bit name
Description
Default
R/W
15:0
reserved
test mode only
0000
res
reg 24- MT933 specific register
Bit
Bit name
Description
Default
R/W
24.15:14
PWRCON[1:0]
Low power controls:
00 = full receive path active. No transmit.
01 = Deep sleep (all off including VREF & OSC)
10 = Sleep (generate MII interrupt on activity)
11 = auto shut down, auto wake on activity
1 = MINT output active high
0 = MINT output active low
1 = disable 10Base-T autopolarity correction
1 = disable SQE in 10Base-T half duplex mode
0 = in case of jabber the 10Base-T will cut the
transmitted frame (normal operation)
1 = Jabber function disable
1 = enable MII loopback in 10Base-T half duplex mode
Force receive regardless of link
Force transmit regardless of link
CRS behavior in full duplex mode:-
0 = CRS is active for transmit only
1= CRS active for receive or transmit
1 = MDIO data accepted without preamble
0 = normal operation
1 = bypass the aligner function
0 = normal operation
1 = bypass the 4B5B encoder function
0 = normal operation
1 = bypass the scrambler function
0 = disable disconnection events
1 = enable disconnect on false carrier detection
Set repeater mode (affects CRS generation)
00
RW
24.13
MINTPOL
0
RW
24.12
24.11
24.10
Pol Dis
SQE disable
JAB disable
0
0
0
RW
RW
RW
24. 9
24.8
24.7
24.6
loop 10
Force RX
Force TX
CRS_CTL
0
0
0
0
RW
RW
RW
RW
24.5
24.4
MF
0
0
RW
RW
Byp ALIGN
24.3
Byp ENC
0
RW
24.2
Byp SCR
0
RW
24.1
DISCEN
0
RW
24:0
RPTR
0
RW
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