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參數(shù)資料
| 型號(hào)： | MT92303 |
| 廠商： | Mitel Networks Corporation |
| 元件分類(lèi)： | Codec |
| 英文描述： | 3.3V Quad Interface, Dual Codec(3.3V 四接口雙編解碼器（提供音頻到PCM的接口）) |
| 中文描述： | 3.3四種接口，雙編解碼器（3.3四接口雙編解碼器（提供音頻到的PCM的接口）） |
| 文件頁(yè)數(shù)： | 13/34頁(yè) |
| 文件大?。?/td> | 166K |
| 代理商： | MT92303 |
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Preliminary Information
MT92303
13
Figure 14 - Microport Waveform (Intel mode)
Figure 15 - Microport Waveform (Motorola/National mode)
Wr
A
0
A
1
A
2
A
3
A
4
A
5
X
CS
SCLK
DATA1
COMMAND/ADDRESS
DATA
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Rd
A
0
A
1
A
2
A
3
A
4
A
5
X
DATA1
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Read
Write
Rd
A
5
A
4
A
3
A
2
A
1
A
0
X
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
CS
SCLK
DATA1
output
X X X X X X X X
DATA2
input
COMMAND/ADDRESS
DATA
Read
Wr
A
5
A
4
A
3
A
2
A
1
A
0
X
X X X X X X X X
DATA1
output
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
DATA2
input
Write
transfer. As shown in Figures 14 and 15 the falling
edge of CS indicates to the MT92303 that a
microport transfer is about to begin. The first 8 clock
cycles of SCLK after the falling edge of CS are
always used to receive the Command/Address byte
from the microcontroller. The Command/Address
byte contains information detailing whether the
second byte transfer will be a read or a write
operation (read = 1, write = 0), and at what address.
The next 8 clock cycles are used to transfer the data
byte between the MT92303 and the microcontroller.
At the end of the two-byte transfer, CS is brought
high again to terminate the session. The rising edge
of CS will tri-state the DATA1 pin. The DATA1 pin will
remain tri-stated as long as CS is high. Intel
processors utilize Least Significant Bit (LSB) first
transmission while Motorola/National processors use
Most Significant Bit (MSB) first transmission. The
MT92303 microport automatically accommodates
these two schemes for normal data bytes. However,
to ensure timely decoding of the R/W and address
information, the Command/Address byte is defined
differently for Intel and Motorola/National operations.
Note
: SCLK needs to be pulsed once after CS is
deactivated at the end of a microport ‘write’. This can
be done by:
Running SCLK continuously.
Reading/Writing to another device (which could
be a dummy) after each microport ‘write’. This
will force SCLK active while CS is high.
Future versions of the MT92303 may not require this
‘extra’ SCLK cycle.
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