參數資料
型號: MT9171AN
廠商: Mitel Networks Corporation
英文描述: ISO2-CMOS ST-BUS⑩ FAMILY Digital Subscriber Interface Circuit Digital Network Interface Circuit
中文描述: ISO2 -意法半導體的CMOS總線⑩家庭數字用戶接口電路的數字網絡接口電路
文件頁數: 13/25頁
文件大?。?/td> 401K
代理商: MT9171AN
Advance Information
MT9171/72
9-127
Table 6. Status Register
Status
Register
Name
Function
0
SYNC
Synchronization
- When set this bit indicates that synchronization to the received
line data sync pattern has been acquired. For DN mode only.
1-2
CHQual
Channel Quality -
These bits provide an estimate of the receiver’s margin against
noise. The farther this 2 bit value is from 0 the better the SNR.
3
Rx
HK
Housekeeping -
This bit is the received housekeeping (HK) bit from the far end.
4-6
Future
Future Functionality.
These bits return Logic 1 when read.
7
ID
This bit provides a hardware identifier for the DNIC revision. The MT9171/72 will
return a logic “0” for this bit. (Logic “1” returned for MT8972A.)
0
1
2
3
4
5
6
7
SYNC
CHQual
Rx HK
Future Functionality
ID
negative going transition indicating a logic "0" and a
positive going transition indicating a logic "1".
There are some major reasons for using a biphase
line code. The power density is concentrated in a
spectral region that minimizes dispersion and
differential attenuation. This can shorten the line
response and reduce the intersymbol interference
which are critical for adaptive echo cancellation.
There are regular zero crossings halfway through
every bit cell or baud which allows simple clock
extraction at the receiving end. There is no D.C.
content in the code so that phantom power feed may
be applied to the line and simple transformer
coupling may be used with no effect on the data. It is
bipolar, making data reception simple and providing
a high signal to noise ratio. The signal is then passed
through a bandpass filter which conditions the signal
for the line by limiting the spectral content from
0.2f
Baud
to 1.6f
Baud
and on to a line driver where it is
made available to be put onto the line biased at V
Bias
.
The resulting transmit signal will have a distributed
spectrum with a peak at 3/4f
Baud
. The transmit signal
(L
OUT
) may be disabled by holding the L
OUT
DIS pin
high or by writing DLO (bit 6) of the Diagnostics
Register to logic “1”. When disabled, L
OUT
is forced to
the V
Bias
level. L
OUT
DIS has an internal pull-down to
allow this pin to be left not connected in applications
where this function is not required. The receive
signal is the above transmit signal superimposed on
the signal from the remote end and any reflections or
delayed symbols of the near end signal.
The frame format of the transmit data on the line is
shown in Figures 11 and 12 for the DN mode at 80
and 160 kbit/s. At 80 kbit/s a SYNC bit for frame
recovery, one bit of the D-channel and the B1-
channel are transmitted. At 160 kbit/s a SYNC bit,
the HK bit, two bits of the D-channel and both B1 and
B2 channels are transmitted.
If the DINB bit of the Control Register is set, the
entire D-channel is transmitted during the B1-
channel timeslot. In MOD mode the SYNC, HK and
D-channel bits are not transmitted or received but
rather a continuous data stream at 80 or 160 kbit/s is
present. No frame recovery information is present on
the line in MOD mode.
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參數描述
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