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參數(shù)資料
| 型號： | MT9171AN |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ISO2-CMOS ST-BUS FAMILY |
| 中文描述： | DATACOM, DIGITAL SLIC, PDSO24 |
| 封裝： | 5.30 MM WIDTH, MO-150AG, SSOP-24 |
| 文件頁數(shù)： | 12/25頁 |
| 文件大?。?/td> | 401K |
| 代理商： | MT9171AN |
MT9171/72
Advance Information
9-126
Table 4a. Default Mode Selection
Notes:
Default Mode 1 can also be selected by tying CDSTi/CDi pin low when DNIC is operating in dual mode.
Default Mode 2 can also be selected by tying CDSTi/CDi pin high when DNIC is operating in dual mode.
Table 5. Diagnostic Register
Notes:
depending upon the status of bit-3.
Do not use L
OUT
to L
IN
loopback in DN/SLV mode.
Do not use DSTo to DSTi loopback in MOD/MAS mode.
When bits 4-7 of the Diagnostic Register are all set to one, the DNIC operates in one of the default modes as defined in Table 4a,
C-Channel
(Bit 0-7)
Internal Control
Register
Internal Diagnostic
Register
Description
XXX01111
00000000
01000000
Default Mode-1
: Bit rate is 80 kbit/s. ATTACK,
PSEN, DINB, DRR and all diagnostics are disabled.
TxHK=0.
Default Mode-2
Bit rate is 160 kbit/s. ATTACK,
PSEN, DINB, DRR and all diagnostics are disabled.
TxHK=0.
XXX11111
00010000
01000000
Bit
Name
Description
0
Reg Sel-1
Register Select-1. Must be set to ’0’ to select the Diagnostic Register.
1
Reg Sel-2
Register Select-2. Must be set to ’1’ to select the Diagnostic Register.
2,3
Loopback
Bit 2
0
0
1
1
Bit 3
0
1
0
1
All loopback testing functions disabled. Normal operation.
DSTi internally looped back into DSTo for system diagnostics.
L
OUT
is internally looped back into L
IN
for system diagnostics.
DSTo is internally looped back into DSTi for end-to-end testing.
4
FUN
Force Unsync. When set to ’1’, the DNIC is forced out-of-sync to test the SYNC
recovery circuitry. When set to ’0’, the operation continues in synchronization.
5
PSWAP
Polynomial Swap. When set to ’1’, the scrambling and descrambling polynomials are
interchanged (use for MAS mode only). When set to ’0’, the polynomials retain their
normal designations.
6
DLO
Disable Line Out. When set to ’1’, the signal on L
OUT
is set set to V
Bias
. When set to
’0’, L
OUT
pin functions normally.
Must be set to ’0’ for normal operation.
7
Not Used
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Reg Sel-1
Reg Sel-2
Loopback
FUN
PSWAP
DLO
Not Used
Default Mode Selection
(Refer to Table 4a)
port operation must be used in MOD mode. The C-
channel is clocked in and out of the CD port by TCK
and CLD with TCK defining the bits and CLD the
channel boundaries of the data stream as shown in
Figure 8.
Line Port (L
IN
, L
OUT
)
The line interface is made up of L
OUT
and L
IN
with
L
OUT
driving the transmit signal onto the line and L
IN
receiving the composite transmit and receive signal
from the line. The line code used in the DNIC is
Biphase and is shown in Figure 10. The scrambled
NRZ data is differentially encoded meaning the
previous differential encoded output is XOR’d with
the current data bit which produces the current
output. This is then biphase encoded where
transitions occur midway through the bit cell with a
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| MT9171AN1 | 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE DNIC 1.5UM - Rail/Tube |
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| MT9171AP1 | 制造商:Microsemi Corporation 功能描述:PB FREE DNIC 1.5UM - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE DNIC 1.5UM - Rail/Tube |
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