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參數(shù)資料
| 型號： | MT91610AQ |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Analog Ringing SLIC |
| 中文描述： | 模擬振鈴用戶接口 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大小： | 251K |
| 代理商： | MT91610AQ |
Preliminary Information
MT91610
5
For convenience, a graph which plots the value of
R2 (K
) versus the approximated loop current is
shown in Figure 6. This graph implies the SLIC is
operating in constant current mode.
As +5V is used as the reference voltage to generate
the loop current, any noise on the +5V rail will
deteriorate the PSR (Power Supply Rejection)
parameter of the SLIC. It is therefore important to
decouple +5V to GND. A 0.1uF cap at Vref pin (pin6)
is recommended.
The
recommended to be between 20mA and 30mA. The
device will automatically switch to voltage fold over
mode should an unexpected long loop situation
occur for a given programmed loop current. The
lowest operational current should be 16mA with
VBAT set at -48V. A typical Operating Current
versus Loop Resistance with VBAT at -48V is shown
in Figure 7. The actually loop current should settle to
within +/- 2 mA of the targeted value.
MT91610
operating
current
mode
is
UD & Line Drivers Overcurrent
Protection
The Line Drivers control the external Battery Feed
circuit which provide power to the line and allows bi-
directional audio transmission.
The loop supervision circuitry provides bias to the
line drivers to feed a constant current. Overcurrent
protection is done by the following steps:
(A) External bipolar transistors to limit the current of
the NPN drivers to 50mA (Figure 5, Q14, Q15, R9,
R19).
(B) The local controller should monitor the
Unbalance Detection output (UD) for any extended
period of assertion (>5 seconds). In such case the
controller should power down the device by
asserting the PD pin, and poll the device every 5
seconds.
The UD output can be used to support GND START
LOOP in a PaBX operation. Reference MSAN-180
for details.
Please note that this UD output should be
disregarded and masked out if RC pin is active (ie
set to +5V).
Powering Up / Down Sequence
AGND is always connected
Powering Up: +5V, -5V, VBAT
PD to +5V for 100ms; PD to 0V
Powering Down: VBAT, -5V, +5V
Balanced Ringing & Automatic Ring
Tripping
Balanced Ringing is applied to the line by setting RC
(pin 30) to +5V and connecting the ringing signal
(20Hz) to RV (pin 35) as shown in Figure 4. A
1.2Vrms input will give approximately 60Vrms output
across Tip and Ring, sufficient for short loop SLIC
applications. The SLIC is capable of detecting an Off
Hook condition during ringing by filtering out the
large A.C. component. A 0.47uF cap should be
connected to pin CP6 (pin 29) to form such filter.
This filter allows a true Off Hook condition to be
monitored at SHK (pin 33). When an Off Hook
condition is detected by the SLIC, it will remove the
20Hz AC ringing voltage and revert to constant
current mode. The local controller will, however, still
need to deselect RC (set it to 0V).
The MT91610 supports short burst of ringing
cadence. A deglitching input (CP7) is provided to
ensure that the SHK pin is glitch free during the
assertion and de-assertion of RC. A 33nF cap should
be connected from this pin to GND.
A positive voltage source is required to be connected
to the DCRI pin (Figure 5) for normal Ringing
operation. The SLIC can perform ringing even with
the DCRI input connected to 0V, however, it does
require the VBAT to be lower than -48V (ie at -53V or
lower) and the 20Hz AC input should be a 2Vrms
square wave.
The MT91610 can also be used in applications
requiring unbalanced ringing using an external relay.
Reference MSAN-180 for details of this and
equations related to ringing.
Line Reversal
The MT91610 can deliver Line Reversal, which is
required in operation such as ANI, by simply setting
LR (pin 7) to +5V. The device transmission
parameters will cease during the reversal. The LR
(pin 7) should be set to 0V for all normal loop
operations.
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