參數資料
型號： MT90870AG2
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Flexible 12 k Digital Switch (F12kDX)
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA272
封裝： 27 X 27 MM, 1.27 MM PITCH, LEAD FREE, PLASTIC, MS-034-BAL-2, BGA-272
文件頁數： 1/86頁
文件大?。?/td> 2093K
代理商： MT90870AG2
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2002-2005, Zarlink Semiconductor Inc. All Rights Reserved.
Features
12,288-channel x 12,288-channel non-blocking
unidirectional switching.The Backplane and
Local inputs and outputs can be combined to
form a non-blocking switching matrix with 48
stream inputs and 48 stream outputs
8,192-channel x 4,096-channel blocking
Backplane to Local stream switch
4,096-channel x 8,192-channel non-blocking
Local to Backplane stream switch
8,192-channel x 8,192-channel non-blocking
Backplane input to Backplane output switch
4,096-channel x 4,096-channel non-blocking
Local input to Local output stream switch
Rate conversion on all data paths, Backplane to
Local, Local to Backplane, Backplane to
Backplane and Local to Local streams
Backplane port accepts 32 ST-BUS streams with
data rates of 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s
or 16.384 Mb/s in any combination, or a fixed
allocation of 16 streams at 32.768 Mb/s
Local port accepts 16 ST-BUS streams with data
rates of 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s or
16.384 Mb/s, in any combination
Per-stream channel and bit delay for Local input
streams
Per-stream channel and bit delay for Backplane
input streams
Per-stream advancement for Local output streams
Per-stream advancement for Backplane output
streams
MT90870
Flexible 12 k Digital Switch (F12kDX)
Data Sheet
Ordering Information
MT90870AG
MT90870AG2
272 Ball PBGA
272 Ball PBGA*
*Pb Free Tin/Silver/Copper
-40 to +85
o
C
Trays
Trays
*Note
: the package thickness is different than the
MT90870AG (see drawing at the end of the data
sheet).
November 2005
Figure 1 - MT90870 Functional Block Diagram
Backplane Data Memories
(8,192 channels)
DS CS R/W A14-A0 DTA D15-D0
Test Port
Microprocessor Interface
and Internal Registers
V
SS (GND)
V
DD_CORE
TDi TDo TCK TRST
TMS
LSTo0-15
(4,096 locations)
RESET
Local
Interface
Connection Memory
BSTi0-31
Backplane
Timing Unit
FP8i
PLL
LSTi0-15
Interface
Backplane
BSTo0-31
Local
C8i
V
DD_IO
LCST0-1
ODE
BCST0-3
C8o
C16o
FP8o
FP16o
V
DD_PLL
Local
Timing
Unit
(8,192 locations)
Connection Memory
Backplane
Interface
Local
Local Data Memories
(4,096 channels)
BORS
LORS
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