參數(shù)資料
型號: MT9046
廠商: Zarlink Semiconductor Inc.
元件分類: 基準電壓源/電流源
英文描述: T1/E1 System Synchronizer with Holdover
中文描述: T1/E1的系統(tǒng)同步的緩繳暫繳稅
文件頁數(shù): 9/34頁
文件大?。?/td> 508K
代理商: MT9046
MT9046
Data Sheet
9
Zarlink Semiconductor Inc.
because the Holdover Mode is very accurate (e.g.,
±
0.2 ppm). Consequently, the phase delay between the input
and output after switching back to Normal Mode is preserved.
State Machine Control
As shown in Figure 1, this state machine controls the Reference Select MUX, the TIE Corrector Circuit and the
DPLL. Control is based on the logic levels at the control inputs RSEL, MS1, MS2 and PCCi (See Figure 6). When
switching from Primary Holdover to Primary Normal, the TIE Corrector Circuit is enabled when PCCi = 1, and
disabled when PCCi = 0.
All state machine changes occur synchronously on the rising edge of F8o. See the Control and Mode of Operation
section for full details.
Figure 6 - Control State Machine Block Diagram
Master Clock
The MT9046 can use either a clock or crystal as the master timing source. For recommended master timing
circuits, see the Applications - Master Clock section.
Control and Mode of Operation
The active reference input (PRI or SEC) is selected by the RSEL pin as shown in Table 2.
RSEL
Input Reference
0
PRI
1
SEC
Table 2 - Input Reference Selection
MS2
MS1
Mode
0
0
NORMAL
0
1
HOLDOVER
1
0
FREERUN
1
1
Reserved
Table 3 - Operating Modes and States
MS1
MS2
To
Reference
Select MUX
To TIE
Corrector
Enable
Control
State Machine
To DPLL
State
Select
PCCi
RSEL
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