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參數(shù)資料
| 型號(hào)： | MT9041B |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | T1/E1 System Synchronizer(T1/E1系統(tǒng)同步裝置（由一個(gè)數(shù)字鎖相環(huán)組成）) |
| 中文描述： | T1/E1的系統(tǒng)同步（T1/E1的系統(tǒng)同步裝置（由一個(gè)數(shù)字鎖相環(huán)組成）） |
| 文件頁(yè)數(shù)： | 3/20頁(yè) |
| 文件大?。?/td> | 87K |
| 代理商： | MT9041B |
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MT9041B
3
19
IC0
Internal Connect.
Connect to Vss
20
IC1
Internal Connect.
Leave open Circuit
21
IC0
Internal Connect.
Connect to Vss
22
IC0
Internal Connect.
Connect to Vss
23
MS
Mode/Control Select (TTL Input).
This pin, determines the device’s state (Normal, or
Freerun) of operation. The logic level at this input is gated in by the rising edge of F8o. See
Table 3.
24
IC0
Internal Connect.
Connect to Vss
25
IC0
Internal Connect.
Connect to Vss
26
FS2
Frequency Select 2 (TTL Input).
This input, in conjunction with FS1, selects which of three
possible frequencies (8kHz, 1.544MHz, or 2.048MHz) may be input to the REF input. See
Table 1.
27
FS1
Frequency Select 1 (TTL Input).
See pin description for FS2.
28
RST
Reset (Schmitt Input).
A logic low at this input resets the MT9041B. To ensure proper
operation, the device must be reset after reference signal frequency changes and power-up.
The RST pin should be held low for a minimum of 300ns. While the RST pin is low, all frame
and clock outputs are at logic high. Following a reset, the input reference source and output
clocks and frame pulses are phase aligned as shown in Figure 10.
Pin Description (continued)
Pin #
Name
Description
Functional Description
The MT9041B is a System Synchronizer, providing
timing (clock) and synchronization (frame) signals to
interface circuits for T1 and E1 Primary Rate Digital
Transmission links.
Figure 1 is a functional block diagram which is
described in the following sections.
Frequency Select MUX Circuit
The MT9041B operates on the falling edges of one
of three possible input reference frequencies (8kHz,
1.544MHz or 2.048MHz). The frequency select
inputs (FS1 and FS2) determine which of the three
frequencies may be used at the reference input
(REF). A reset (RST) must be performed after every
frequency select input change. Operation with FS1
and FS2 both at logic low is reserved and must not
be used. See Table 1.
Table 1 - Input Frequency Selection
Digital Phase Lock Loop (DPLL)
The DPLL of the MT9041B consists of a Phase
Detector, Limiter, Loop Filter, Digitally Controlled
Oscillator, and a Control Circuit (see Figure 3).
Phase Detector
- the Phase Detector compares the
primary reference signal (REF) with the feedback
signal from the Frequency Select MUX circuit, and
provides an error signal corresponding to the phase
difference between the two. This error signal is
passed to the Limiter circuit. The Frequency Select
MUX allows the proper feedback signal to be
externally
selected
(e.g.,
2.048MHz).
8kHz,
1.544MHz
or
Limiter
- the Limiter receives the error signal from
the Phase Detector and ensures that the DPLL
responds to all input transient conditions with a
maximum output phase slope of 5ns per 125us. This
FS2
FS1
Input Frequency
0
0
Reserved
0
1
8kHz
1
0
1.544MHz
1
1
2.048MHz
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9041BP | 制造商:Microsemi Corporation 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述:PCM, OTHER/SPECIAL/MISCELLANEOUS, 28 Pin, Plastic, PLCC |
| MT9041BP1 | 制造商:Microsemi Corporation 功能描述:FRAMER E1 /T1 5V 28PLCC - Rail/Tube 制造商:Microsemi Corporation 功能描述:PB FREE MULTIPLE OUTPUT TRUNK PLL 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1 /T1 5V 28PLCC - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE MULTIPLE OUTPUT TRUNK PLL |
| MT9041BPR | 制造商:Microsemi Corporation 功能描述:SPECIALTY TELECOM CIRCUIT, 28 Pin Plastic PLCC |
| MT9041BPR1 | 制造商:Microsemi Corporation 功能描述:FRAMER E1 /T1 5V 28PLCC - Tape and Reel 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1 /T1 5V 28PLCC - Tape and Reel |
| MT9042 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Global Digital Trunk Synchronizer |
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