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| 型號(hào)： | MT8LLN21PADF |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA728 |
| 封裝： | FLIP CHIP, PLASTIC, BGA-728 |
| 文件頁(yè)數(shù)： | 1/138頁(yè) |
| 文件大小： | 2301K |
| 代理商： | MT8LLN21PADF |
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21Pad Host Controller
MT8LLN21PADF.fm – Rev. 1, Pub. 2/02
1
2002, Micron Technology Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
ADVANCE
21PAD
HOST CONTROLLER
FEATURE OVERVIEW
Supports up to two Intel Pentium III [80533/
80530 family] at 133 MHz front side bus frequency
Up to 8 GB/s of PC1600/PC2100 DDR SDRAM
64-bit, 33/66 MHz PCI bus
64-bit, 66/100/133 MHz PCI-X bus
SMBus port for remote maintenance
Error reporting status preserved on warm-boot
Multiple Controller support for more memory and
I/O capacity
FEATURES
Memory Interface: 8GB DDR SDRAM
– PC2100 supported with a 133 MHz front side bus
– PC1600 supported with a 133 MHz front side bus
– Maximum bandwidth of 2.1 GB/s
– 72-bit data bus with ECC (single-bit correct, mul-
tiple-bit detect) and hardware scrubbing
– Supports up to four registered or two
unbuffered DIMMs
– Hardware memory initialization
– 64, 128, 256, and 512 Mb memory technology
support
Processor Interface
– Intel Pentium III 80533/80530 processor family
– 133 MHz front side bus
– Front side bus data ECC
– Parity on all front side bus control signals
– Redundant bus timeout detection
– 36-bit addressing
– Support for single and multiple processor designs
PCI Bus Interface
– 64-bit PCI bus operating at 33/66 MHz
– Compliant with PCI local bus specification
revision 2.2
– Supports up to seven PCI master devices
– Cache-line write assembly for Host-PCI transfers
– Both delayed and deferred READ support for
Host-PCI transfers
– PCI dual address transaction support
– Write request clumping for PCI-memory transfers
to improve memory utilization.
– Prefetch READs for PCI-memory transfers
– Delayed read support for PCI-memory
transactions
– Fencing protocol for efficient transaction
ordering
PCI-X Interface
– 64-bit PCI-X bus operating at 66/100/133 MHz
– Direct access to memory for low latency and max-
imum bandwidth
– Individual concurrent master and target sections
with relaxed ordering for maximum concurrency
– Support for multiple outstanding split- request/
split-completions in both upstream and down-
stream directions
– Compliant with PCI-X Addendum to the PCI Local
Bus specification revision 1.0
Internal switch architecture
– Up to 6.3 GB/s internal interconnect with maxi-
mum concurrency
– Distributed buffering and arbitration
– Separate request, read data, and write data paths
SMBus Interface
– Allows remote read/write access to internal con-
figuration registers
Power Management
– Compliant with APM 1.2, ACPI 2.0
– Suspend-to-RAM support to place DDR SDRAM
in self-refresh
Package
– 728-pin FC-PBGA
21 PAD
Host Controller
MT8LLN21PADF
For the latest data sheet please refer to the Micron Web
site: www.micron.com/chipset.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8LLN21PADF-A | 制造商:Micron Technology Inc 功能描述:COPPERHEAD CHIPSET - Trays |
| MT8LLN21PADFA2 | 制造商:Micron Technology Inc 功能描述:COPPERHEAD CHIP 制造商:Micron Technology 功能描述:COPPERHEAD CHIP |
| MT8LLN21PADF-A2 | 制造商:Micron Technology Inc 功能描述:COPPERHEAD CHIP 制造商:Micron Technology 功能描述:COPPERHEAD CHIP |
| MT8LLN22NCNE-A | 制造商:Micron Technology Inc 功能描述:COPPERTAIL CHIPSET - Trays |
| MT8LLN22NCNE-A2 | 制造商:Micron Technology Inc 功能描述:COPPERTAIL CHIPSET AND MOTHERBOARD - Trays |
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