參數(shù)資料
型號(hào)： MT8985APR1
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Enhanced Digital Switch
中文描述： TELECOM, DIGITAL TIME SWITCH, PQCC44
封裝： LEAD FREE, PLASTIC, MS-018AC, LCC-44
文件頁(yè)數(shù)： 4/26頁(yè)
文件大?。?/td> 568K
代理商： MT8985APR1
MT8985
Data Sheet
4
Zarlink Semiconductor Inc.
Functional Description
With the integration of voice, video and data services into the same network, there has been an increasing demand
for systems which ensure that data at N x 64 Kbit/s rates maintain frame sequence integrity while being transported
through time slot interchange circuits. Existing requirements demand time slot interchange devices performing
switching with constant throughput delay while guaranteeing minimum delay for voice channels.
The MT8985 device provides both functions and allows existing systems based on the MT8980D to be easily
upgraded to maintain the data integrity while multiple channel data are transported. The device is designed to
switch 64 kbit/s PCM or N x 64 kbit/s data. The MT8985 can provide both frame integrity for data applications and
minimum throughput switching delay for voice applications on a per channel basis.
By using Zarlink Message mode capability, the microprocessor can access input and output time slots on a per
channel basis to control devices such as the Zarlink MT8972, ISDN Transceivers and T1/CEPT trunk interfaces
through the ST-BUS interface. Different digital backplanes can be accepted by the MT8985 device without user's
intervention. The MT8985 device provides an internal circuit that automatically identifies the polarity and format of
frame synchronization input signals compatible to ST-BUS and GCI interfaces.
Device Operation
A functional block diagram of the MT8985 device is shown in Figure 1. The serial ST-BUS streams operate
continuously at 2.048 Mb/s and are arranged in 125
μ
s wide frames each containing 32 8-bit channels. Eight input
(STi0-7) and eight output (STo0-7) serial streams are provided in the MT8985 device allowing a complete 256 x 256
channel non-blocking switch matrix to be constructed. The serial interface clock for the device is 4.096 MHz, as
required in ST-BUS and GCI specifications.
Data Memory
The received serial data is converted to parallel format by the on-chip serial to parallel converters and stored
sequentially in a 256-position Data Memory. The sequential addressing of the Data Memory is generated by an
internal counter that is reset by the input 8 kHz frame pulse (F0i) marking the frame boundaries of the incoming
serial data streams.
Depending on the type of information to be switched, the MT8985 device can be programmed to perform time slot
interchange functions with different throughput delay capabilities on a per-channel basis. For voice applications, the
variable delay mode can be selected ensuring minimum throughput delay between input and output data. In
multiple or grouped channel data applications, the constant delay mode can be selected maintaining the integrity of
the information through the switch.
Data to be output on the serial streams may come from two sources: Data Memory or Connect Memory. Locations
in the Connect Memory, which is split into HIGH and LOW parts, are associated with particular ST-BUS output
streams. When a channel is due to be transmitted on an ST-BUS output, the data for the channel can either be
switched from an ST-BUS input (connection mode) or it can be originated from the microprocessor (message
mode). If a channel is configured in connection mode, the source of the output data is the Data Memory. If a
channel is configured in message mode, the source of the output data is the Connect Memory Low. Data destined
for a particular channel on the serial output stream is read from the Data or Connect Memory Low during the
previous channel time slot. This allows enough time for memory access and internal parallel to serial conversion.
Connection and Message Modes
In connection mode, the addresses of input source for all output channels are stored in the Connect memory Low.
The Connect Memory Low locations are mapped to each location corresponding to an output 64 kb/s channel. The
contents of the Data memory at the selected address are then transferred to the parallel to serial converters. By
having the output channel to specify the input channel through the connect memory, the user can route the same
input channel to several output channels, allowing broadcasting facility in the switch.
相關(guān)PDF資料
PDF描述
MT8985AP1 Enhanced Digital Switch
MT8985 CMOS ST-BUS⑩ FAMILY Enhanced Digital Switch
MT8985AE CMOS ST-BUS⑩ FAMILY Enhanced Digital Switch
MT8985AL CMOS ST-BUS⑩ FAMILY Enhanced Digital Switch
MT8985AP CMOS ST-BUS⑩ FAMILY Enhanced Digital Switch
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT8986 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multiple Rate Digital Switch
MT8986AC 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Multiple Rate Digital Switch
MT8986AE 制造商:Microsemi Corporation 功能描述:
MT8986AE1 制造商:Microsemi Corporation 功能描述:PB FREE MULTIPLE RATE DIGITAL SWITCH 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 256 X 256/512 X 256/128 X 128 131.072MBPS 5V 40P - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM/TSI SWITCH 512X256 40PDIP 制造商:Microsemi Corporation 功能描述:IC TDM/TSI SWITCH 512X256 40PDIP
MT8986AL 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 256 X 256/512 X 256/128 X 128 131.072MBPS 5V 44M - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 256 X 256/512 X 256/128 X 128 131.072MBPS 5V 44M - Trays
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