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參數(shù)資料
| 型號(hào)： | MT8985AP |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | CMOS ST-BUS⑩ FAMILY Enhanced Digital Switch |
| 中文描述： | 意法半導(dǎo)體的CMOS總線⑩家庭增強(qiáng)型數(shù)字交換機(jī) |
| 文件頁數(shù)： | 5/26頁 |
| 文件大?。?/td> | 568K |
| 代理商： | MT8985AP |
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MT8985
Data Sheet
5
Zarlink Semiconductor Inc.
In message mode the CPU writes data to the Connect Memory Low locations which correspond to the output link
and channel number. The contents of the Connect Memory Low are transferred to the parallel to serial converter
one channel before it is to be output. The Connect Memory Low data is transmitted each frame to the output until it
is changed by the CPU.
The per-channel functions available in the MT8985 are controlled by the Connect Memory High bits, which
determine whether individual output channels are selected into specific conditions such as: message or connection
mode, variable or constant throughput delay modes, output drivers enabled or in three-state condition. In addition,
the Connect Memory High provides one bit to allow the user to control the state of the CSTo output pin.
If an output channel is set to three-state condition, the TDM serial stream output will be placed in high impedance
during that channel time. In addition to the per-channel three-state control, all channels on the TDM outputs can be
placed in high impedance at one time by pulling the ODE input pin in LOW. This overrides the individual per-
channel programming on the Connect Memory High bits.
The Connect Memory data is received via the Microprocessor Interface at D0-D7 lines. The addressing of the
MT8985 internal registers, Data and Connect memories is performed through address input pins and some bits of
the device's Control register. The higher order address bits come from the Control register, which may be written or
read through the microprocessor interface. The lower order address bits come directly from the external address
line inputs. For details on the device addressing, see Software Control and Control register description.
Serial Interface Timing
The MT8985 master clock (C4i) is a 4.096 MHz allowing serial data link configuration at 2.048 Mb/s to be
implemented. The MT8985 frame synchronization pulse can be formatted according to ST-BUS or GCI interface
specifications; i.e., the frame pulse can be active in HIGH (GCI) or LOW (ST-BUS). The MT8985 device
automatically detects the presence of an input frame pulse and identifies the type of backplane present on the serial
interface. Upon determining the correct interface connected to the serial port, the internal timing unit establishes the
appropriate serial data bit transmit and sampling edges. In ST-BUS mode, every second falling edge of the 4.096
MHz clock marks a bit boundary and the input data is clocked in by the rising edge, three quarters of the way into
the bit cell. In GCI mode, every second rising edge of the 4.096 MHz clock marks the bit boundary while data
sampling is performed during the falling edge, at three quarters of the bit boundaries.
Delay through the MT8985
The transfer of information from the input serial streams to the output serial streams results in a delay through the
MT8985 device. The delay through the MT8985 device varies according to the mode selected in the V/C bit of the
connect memory high.
Variable Delay Mode
The delay in this mode is dependent only on the combination of source and destination channels and it is not
dependent on the input and output streams. The minimum delay achievable in the MT8985 device is 3 time slots. In
the MT8985 device, the information that is to be output in the same channel position as the information is input
(position n), relative to frame pulse, will be output in the following frame (channel n, frame n+1). The same occurs if
the input channel has to be output in the two channels succeeding (n+1 and n+2) the channel position as the
information is input.
The information switched to the third timeslot after the input has entered the device (for instance, input channel 0 to
output channel 3 or input channel 30 to output channel 1), is always output three channels later.
Any switching configuration that provides three or more timeslots between input and output channels, will have a
throughput delay equal to the difference between the output and input channels; i.e., the throughput delay will be
less than one frame. Table 1 shows the possible delays for the MT8985 device in Variable Delay mode:
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT8985 | Enhanced Digital Switch |
| MT8986 | Multiple Rate Digital Switch |
| MT8986AE | CMOS ST-BUS Family Multiple Rate Digital Switch |
| MT8986APR1 | CMOS ST-BUS Family Multiple Rate Digital Switch |
| MT8986APR | CMOS ST-BUS Family Multiple Rate Digital Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8985AP1 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 256 X 256 16.384MBPS 5V 44PLCC /BAKE/DRYPACK - Rail/Tube 制造商:Microsemi Corporation 功能描述:ENHANCED DIGITAL SWITCH 制造商:Zarlink Semiconductor Inc 功能描述:ENHANCED DIGITAL SWITCH |
| MT8985APR | 制造商:Microsemi Corporation 功能描述: |
| MT8985APR1 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 256 X 256 16.384MBPS 5V 44PLCC - Tape and Reel 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM/TSI SWITCH 256X256 44PLCC 制造商:Microsemi Corporation 功能描述:IC TDM/TSI SWITCH 256X256 44PLCC |
| MT8986 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multiple Rate Digital Switch |
| MT8986AC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Multiple Rate Digital Switch |
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