參數(shù)資料
型號(hào): MT8981DP
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Digital Switch
中文描述: TELECOM, DIGITAL TIME SWITCH, PQCC44
封裝: PLASTIC, MS-018AC, LCC-44
文件頁(yè)數(shù): 8/17頁(yè)
文件大?。?/td> 561K
代理商: MT8981DP
MT8981D
ISO-CMOS
2-24
Figure 8 - Example Architecture of a Simple Digital Switching System
Controlling
Micro-
Processor
Speech
Switch
-
8981
Control &
Signalling
-
8981
STo0-3
STi0-3
STo0-3
Line Interface Circuit
with Codec (e.g. 8964)
Line 1
Line 128
Line Interface Circuit
with Codec (e.g. 8964)
4
4
4
4
Repeated for Lines
2 to 127
Repeated for Lines
2 to 127
STi0-3
Application Circuit with 6802 Processor
Fig. 10 shows an example of a complete circuit
which may be used to evaluate the chip.
For convenience, a 4 MHz crystal oscillator has been
used rather than a 4.096 MHz clock, as both are
within the limits of the chip’s specifications. The RC
delay used with the 393 counters ensures a
sufficient hold time for the FP signal, but the values
used may have to be changed if faster 393 counters
become available.
The chip is shown as memory mapped into the
MEK6802D3
system.
Chip
correspond to processor addresses 2000-203F.
Delay through the address decoder requires the
VMA signal to be used twice to remove glitches. The
MEK6802D3 board uses a 10K
pin, which would have to be incorporated into the
circuit if the board was replaced by a processor.
addresses
00-3F
pullup on the MR
Figure 9 - Four 8981s Arranged in a Non-Blocking 8 x 8 Configuration
IN 0/3
IN 4/7
8981
#1
STi0/3 STo0/3
8981
#2
STi0/3 STo0/3
8981
#3
STi0/3 STo0/3
8981
#4
STi0/3 STo0/3
OUT 0/3
OUT 4/7
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