參數(shù)資料
型號: MT8981DP
廠商: Mitel Networks Corporation
英文描述: ISO-CMOS ST-BUS⑩ FAMILY Digital Switch
中文描述: 異意法半導(dǎo)體的CMOS總線⑩家庭數(shù)字開關(guān)
文件頁數(shù): 13/20頁
文件大?。?/td> 481K
代理商: MT8981DP
MT8981D
Data Sheet
13
Zarlink Semiconductor Inc.
Figure 11 - Output Test Load
Timing is over recommended temperature & power supply voltages
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
* Contents of Connection Memory are not lost if the clock stops, however, ST-BUS outputs go into the high impedance state.
NB:
Frame Pulse is repeated every 512 cycles of C4i.
Figure 12 - Frame Alignment
AC Electrical Characteristics
- Clock Timing (Figures 12 and 13)
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
I
N
P
U
T
S
Clock Period*
t
CLK
220
244
300
ns
2
Clock Width High
t
CH
95
122
150
ns
3
Clock Width Low
t
CL
110
122
150
ns
4
Clock Transition Time
t
CTT
20
ns
5
Frame Pulse Setup Time
t
FPS
20
200
ns
6
Frame Pulse Hold Time
t
FPH
0.020
50
μ
s
7
Frame Pulse Width
t
FPW
244
ns
Output
Pin
Test Point
C
L
V
SS
S1
R
L
V
DD
S2
V
SS
S1 is open circuit except
when testing output levels
or high impedance states.
S2 is switched to V
or
V
SS
when testing output
levels or high impedance
states.
C4i
F0i
BIT
CELLS
Channel 31
Bit o
Channel 0
Bit 7
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