參數(shù)資料
型號(hào)： MT8926AP
廠商： Mitel Networks Corporation
英文描述： ISO-CMOS ST-BUS⑩ FAMILY T1 Performance Monitoring Adjunct Circuit (PMAC)
中文描述： 異意法半導(dǎo)體的CMOS總線⑩家庭T1性能監(jiān)控兼任電路（PMAC下）
文件頁(yè)數(shù)： 10/26頁(yè)
文件大?。?/td> 309K
代理商： MT8926AP
4-12
MT8926
s
Table 7. Framing Bits which Affect the SE and
FE Counters
framing pattern. Refer to Table 18 for the ESF
framing pattern.
Table 7 illustrates which framing bits are included in
the framing error calculations in SF and ESF modes
with the Framing Pattern Selection bit (FSel), CSTi1
channel 11 bit 3, high and low. Bits marked "1" or "0"
are counted, bits marked "X" are excluded.
When an SF signal is being received and FSel is low
the counters are incremented by F
T
framing bit error
events. FSel must be high for the extended
superframe FPS bits or both SF F
T
and F
S
bits to be
included. It should be noted that the twelfth SF
framing bit (the sixth F
S
framing bit) is excluded
because it can be used as an SF alternate yellow
alarm. The ALRM bit of the Master Status Word 1
(CSTo channel 15 bit 5) will be high if the received
alternate yellow alarm bit is high. The ALRM bit will
always be low if FSel is low.
The FE and SE counters will wrap around to 0000
after reaching a terminal count of 1111. When the FE
Framing Select
SF (F
T)
SF (F
S)
ESF (FPS)
FSel=0
101010 XXXXXX
XXXXXX
FSel=1
101010
00111X
001011
counter wraps around the Framing Error Saturation
Indication bit (FSI) will be set, Table 11, and a G2
interrupt will be asserted. The Severely Errored
Framing Event Indication bit (SEI), Table 11, will be
set when the SE counter is incremented. This will
also assert a G2 interrupt. These counters are frozen
when
the
PMAC
or
synchronization (i.e., CSTo Channel 7 bit 2, FECV =
0).
MT8976/77
has
lost
The SE and FE counters, as well as the SEI and FSI
bits are cleared by a high-to-low transition of bit 7,
SE Counter Reset (SER), and bit 6, FE Counter
Reset (FER), of the PMAC Control Word channel 11
CSTi1.
BPV and CRC-6 Error Counters
The MT8926 has two eight bit counters, the Bipolar
Violation Counter (BPV), Table 10, and the CRC-6
Framing Error Counter (CRC), Table 9. The BPV
counter is incremented each time a non-B8ZS
bipolar code violation is received on the T1 interface.
The PMAC performs B8ZS recovery of the receive
data before BPVs are detected. The CRC-6 Framing
Error Counter is incremented when the least
significant bit of the MT8976/77 CRC error counter is
incremented.
The BPV and CRC counters will wrap around to
00000000 after reaching a terminal count of
Table 8. Framing Error and Severely Errored Framing Event Counters (CSTo Channel 19)
Bit
Name
Description
7-4
SE
Severely Errored Framing Event. This four bit counter is incremented when the
MT8926 detects two out of six framing bit errors. It will wrap around after reaching
terminal count and can be reset by toggling bit 7 of the PMAC Control Word (Table
14, CSTi1 channel 11) from high to low.
When receiving a SF T1 signal, both F
S
and F
T
bit errors are counted if bit 3 in the
PMAC Control Word is set high. If this bit is set low, only errors in the F
T
bits will be
counted. When both F
S
and F
T
bit errors are counted, F
S
bit 6 (in the twelfth frame in
an SF superframe) is not examined for errors because it can be used to indicate a
Yellow alarm.
3-0
FE
Framing Error Count. This four bit counter is incremented when a framing bit error is
detected.
When receiving a SF T1 signal, both F
S
and F
T
bit errors are counted if bit 3 in the
PMAC Control Word is set high. If this bit is set low, only errors in the F
T
bits will be
counted. When both F
S
and F
T
bit errors are counted, F
S
bit 6 (in the twelfth frame in
an SF superframe) is not examined for errors because it can be used to indicate a
Yellow alarm.
The counter shall wrap around after reaching terminal count and can be reset by
toggling bit 6 in the PMAC Control Word (Table 14, CSTi1 channel 11) from high to
low.
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