參數資料
型號: MT8910-1AP
廠商: Mitel Networks Corporation
英文描述: CMOS ST-BUS⑩ FAMILY Digital Subscriber Line Interface Circuit
中文描述: 意法半導體的CMOS總線⑩家庭數字用戶線接口電路
文件頁數: 14/26頁
文件大?。?/td> 419K
代理商: MT8910-1AP
MT8910-1
Preliminary Information
9-16
Control Register 3
Setting CRS1 and CRS0 to 1, 0, respectively, routes
the input C-channel to Control Register 3, allowing
access to the transmit M-bits as shown in Table 4.
The transmit M-channel is a 4 kbit/s maintenance
channel which may carry the EOC messages (with
overhead) as specified in T1.601-1988. Except for
the CRC bits, the M-bits are treated as a transparent
data channel through the DSLIC. CRC bits will be
generated by the transceiver and will be inserted into
the M-channel during their respective M-bit time
slots. (This implies that all input M-bits which are
defined as CRC bits will be overwritten by the
transceiver.) Structuring of the M-bits is described in
the “Maintenance Channel" section of the functional
description.
Control Words After Reset
Applying a logic low to the MRST pin will result in the
three control registers assuming a reset state.
Following a master reset, the three Control Registers
will take the following states:
Control Register 1:
C7
0
C6
0
C5
1
C4
0
C3
0
C2
0
C1
0
C0
0
Status Register 1
When SRID1=0 and SRID0=0, the contents of
Status Register 1 are being output in the C-channel
allowing the system to monitor the functions
described below. (Refer to Table 5.)
Bits 7 and 6 of Status Register 1, SRID1 and SRID0,
are used to identify which status register is being
carried in the output C-channel. These bits are
encoded as follows:
SRID1
0
0
1
1
SRID0
0
1
0
1
Definition
Status Register 1
Status Register 2
Status Register 3
Status Register 4
Control Register 2:
C7
0
C6
0
C5
0
C4
0
C3
0
C2
0
C1
0
C0
1
Control Register 3:
C7
1
C6
1
C5
1
C4
1
C3
1
C2
1
C1
1
C0
0
Table 5. Status Register 1
Bit
Name
Description
7,6
SRID1, SRID0
Status Register ID. Always reads 0,0 when Status Register 1 is output.
5,4,3
IS2, IS1, IS0
Internal State Indication.
IS2
IS1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
IS0
0
1
0
1
0
1
0
1
Definition
Full Reset State
Training with no Basic Frame Sync
Training with Basic Frame Sync but no Superframe Sync
Training with Basic Frame Sync and Superframe Sync
Loss of synchronization after E.C. has converged
NA
Loss of superframe sync after E.C. has converged
Active State
2
RxSFIB
Received superframe Indication. When low, indicates the beginning of the received superframe.
This bit is low for one ST-BUS frame, then high for 95 ST-BUS frames.
1
RSV
Reserved. Always read a 0.
0
CRCERR
When “1”, the received CRC code did not match with a locally generated CRC code, indicating
that the received data included an error. When “0”, the received CRC code matched with the
internally generated CRC.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SRID1
SRID0
IS2
IS1
IS0
RxSFIB
RSV
CRCERR
相關PDF資料
PDF描述
MT8920 ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit
MT8920B ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit
MT8920B-1 ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit
MT8920BC ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit
MT8920BE ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit
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