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參數(shù)資料
| 型號： | MT8910-1 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | CMOS ST-BUS⑩ FAMILY Digital Subscriber Line Interface Circuit |
| 中文描述： | 意法半導(dǎo)體的CMOS總線⑩家庭數(shù)字用戶線接口電路 |
| 文件頁數(shù)： | 6/26頁 |
| 文件大?。?/td> | 419K |
| 代理商： | MT8910-1 |
MT8910-1
Preliminary Information
9-8
Figure 4 - Frame Structure
12 ms
1.5 ms
50
μ
s
50
μ
s
12.5
μ
s
Superframe
Frame
Information
Channels
Corresponding
ST-BUS
Frame 1
Frame 2
Frame 3
Frame 4
Frame 5
Frame 6
Frame 7
Frame 8
SW
2B + D
2B + D
2B + D
2B + D
2B + D
2B + D 2B + D
2B + D
2B + D 2B + D
2B + D
2B + D
M
B11 B12
B13 B14
B15 B16
B17
B18 B21
B22
B23
B24 B25 B26
B27
B28
D1
D2
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
D0
D1
Basic Frame Synchronization (BFS) is achieved
using the algorithm shown in Figure 5. The DSLIC
searches for the sync word or the inverted sync word
within the received data stream. After detecting
three consecutive synchronization patterns spaced
exactly 120 quats apart, the DSLIC declares terminal
synchronization by setting the bits of the Internal
State Indicator to 111 in Status Register 1. A loss of
synchronization is declared by the DSLIC when at
least one of the nine quats at the beginning of each
Basic Frame differs by more than one quantization
level for two consecutive frames.
A search for superframe synchronization will begin
only after Basic Frame sync has been found. The
DSLIC will declare superframe sync (SFS) on the
first occurrence of the properly spaced Inverted Sync
Word (ISW) once Basic Frame sync has been
acquired. The synchronized state is identified by the
status of internal state bits IS2, IS1 and IS0 found in
Status Register 1.
The DSLIC will lose superframe sync under three
conditions;
1)
if the DSLIC loses basic frame sync,
2)
frames apart,
if the ISW does not occur exactly eight basic
3)
if the ISW is received when it is not expected.
Activation/Deactivation
The DSLIC has a complete activation/deactivation
state machine which allows the user to activate or
deactivate the link as per the requirements in the
Figure 5 - Frame Synchronization State Diagram
STATE : LOST
BFS : 0
One
Valid
SW
Error in
SW
STATE : SENSING1
BFS : 0
One
Valid
SW
STATE : SENSING2
BFS : 0
One Valid SW
> One-Level Error in SW
STATE : LOSING
BFS : 1
> One-Level
Error in SW
Valid
SW
STATE : SYNC
BFS : 1
Error in
SW
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT8910-1AC | CMOS ST-BUS⑩ FAMILY Digital Subscriber Line Interface Circuit |
| MT8910-1AP | CMOS ST-BUS⑩ FAMILY Digital Subscriber Line Interface Circuit |
| MT8920 | ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
| MT8920B | ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
| MT8920B-1 | ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8910-1AC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Digital Subscriber Line Interface Circuit |
| MT8910-1AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Digital Subscriber Line Interface Circuit |
| MT8920 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
| MT8920AE | 制造商:Mitel Networks Corporation 功能描述: |
| MT8920B | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
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