參數(shù)資料
型號: MT88L70AN
廠商: Mitel Networks Corporation
英文描述: 3 Volt Integrated DTMF Receiver
中文描述: 3伏集成雙音多頻接收器
文件頁數(shù): 11/16頁
文件大?。?/td> 474K
代理商: MT88L70AN
MT88L70
Data Sheet
11
Zarlink Semiconductor Inc.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
*NOTES:
1. Used for guard-time calculation purposes only and tested at -4 dBm.
2. These, user adjustable parameters, are not device specifications. The adjustable settings of these minimums and maximums are
recommendations based upon network requirements.
3. With valid tone present at input, t
PU
equals time from PDWN going low until ESt going high.
AC Electrical Characteristics
- V
DD
= 3.0 V+20%/-10%, V
SS
= 0 V, -40
°
C
To
+85
°
C, using Test Circuit shown in Figure 6.
Characteristics
Sym.
Min.
Typ.
Max.
Units
Conditions
1
T
I
M
I
N
G
Tone present detect time
t
DP
5
11
14
ms
Note 1
2
Tone absent detect time
t
DA
0.5
4
8.5
ms
Note 1
3
Tone duration accept
t
REC
40
ms
Note 2
4
Tone duration reject
t
REC
20
ms
Note 2
5
Interdigit pause accept
t
ID
40
ms
Note 2
6
Interdigit pause reject
t
DO
20
ms
Note 2
7
O
U
T
P
U
T
S
Propagation delay (St to Q)
t
PQ
11
μ
s
μ
s
TOE=V
DD
8
Propagation delay (St to StD)
t
PStD
20
TOE=V
DD
9
Output data set up (Q to StD)
t
QStD
5.0
μ
s
TOE=V
DD
load of 10 k
,
50 pF
10
Propagation delay (TOE to Q ENABLE)
t
PTE
50
ns
11
Propagation delay (TOE to Q DISABLE)
t
PTD
130
ns
load of 10 k
,
50 pF
12
P
D
W
N
Power-up time
t
PU
30
ms
Note 3
13
Power-down time
t
PD
20
ms
14
C
L
O
C
K
Crystal/clock frequency
f
C
3.5759 3.5795
3.5831
MHz
15
Clock input rise time
t
LHCL
110
ns
Ext. clock
16
Clock input fall time
t
HLCL
110
ns
Ext. clock
17
Clock input duty cycle
DC
CL
40
50
60
%
Ext. clock
18
Capacitive load (OSC2)
C
LO
15
pF
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