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參數(shù)資料
| 型號： | MT88L70 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | 3 Volt Integrated DTMF Receiver(3V 集成雙音多頻信號（DTMF）接收器) |
| 中文描述： | 3伏集成雙音多頻接收器（3V的集成雙音多頻信號（DTMF）的接收器） |
| 文件頁數(shù)： | 3/15頁 |
| 文件大小： | 101K |
| 代理商： | MT88L70 |
MT88L70
4-25
Functional Description
The MT88L70 monolithic DTMF receiver offers small
size, low power consumption and high performance,
with 3 volt operation. Its architecture consists of a
bandsplit filter section, which separates the high and
low group tones, followed by a digital counting
section which verifies the frequency and duration of
the received tones before passing the corresponding
code to the output bus.
Filter Section
Separation of the low-group and high group tones is
achieved by applying the DTMF signal to the inputs
of two sixth-order switched capacitor bandpass
filters, the bandwidths of which correspond to the low
and high group frequencies. The filter section also
incorporates notches at 350 and 440 Hz for
exceptional dial tone rejection. Each filter output is
followed by a single order switched capacitor filter
section which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators
which are provided with hysteresis to prevent
detection of unwanted low-level signals. The outputs
of the comparators provide full rail logic swings at the
frequencies of the incoming DTMF signals.
Decoder Section
Following the filter section is a decoder employing
digital counting techniques to determine the
frequencies of the incoming tones and to verify that
they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by extraneous signals such as voice while
providing tolerance to small frequency deviations
and variations. This averaging algorithm has been
developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of
interfering frequencies (third tones) and noise. When
the detector recognizes the presence of two valid
tones (this is referred to as the “signal condition” in
some industry specifications) the “Early Steering”
(ESt) output will go to an active state. Any
subsequent loss of signal condition will cause ESt to
assume an inactive state (see “Steering Circuit”).
Steering Circuit
Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred to
as character recognition condition). This check is
performed by an external RC time constant driven by
ESt. A logic high on ESt causes v
c
(see Figure 3) to
rise as the capacitor discharges. Provided signal
condition is maintained (ESt remains high) for the
Table 1. Functional Decode Table
L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE
X = DON‘T CARE
validation period (t
GTP
), v
c
reaches the threshold
(V
TSt
) of the steering logic to register the tone pair,
latching its corresponding 4-bit code (see Table 1)
into the output latch. At this point the GT output is
activated and drives v
c
to V
DD
. GT continues to drive
high as long as ESt remains high. Finally, after a
short delay to allow the output latch to settle, the
delayed steering output flag (StD) goes high,
signalling that a received tone pair has been
registered. The contents of the output latch are
made available on the 4-bit output bus by raising the
three state control input (TOE) to a logic high. The
steering circuit works in reverse to validate the
interdigit pause between signals. Thus, as well as
rejecting signals too short to be considered valid, the
receiver will tolerate signal interruptions (dropout)
too short to be considered a valid pause. This facility,
together with the capability of selecting the steering
time constants externally, allows the designer to
tailor performance to meet a wide variety of system
requirements.
Guard Time Adjustment
In many situations not requiring selection of tone
duration and interdigital pause, the simple steering
circuit shown in Figure 3 is applicable. Component
values are chosen according to the formula:
Digit
TOE
INH
ESt
Q
4
Q
3
Q
2
Q
1
ANY
L
X
H
Z
Z
Z
Z
1
H
X
H
0
0
0
1
2
H
X
H
0
0
1
0
3
H
X
H
0
0
1
1
4
H
X
H
0
1
0
0
5
H
X
H
0
1
0
1
6
H
X
H
0
1
1
0
7
H
X
H
0
1
1
1
8
H
X
H
1
0
0
0
9
H
X
H
1
0
0
1
0
H
X
H
1
0
1
0
*
H
X
H
1
0
1
1
#
H
X
H
1
1
0
0
A
H
L
H
1
1
0
1
B
H
L
H
1
1
1
0
C
H
L
H
1
1
1
1
D
H
L
H
0
0
0
0
A
H
H
L
undetected, the output code
will remain the same as the
previous detected code
B
H
H
L
C
H
H
L
D
H
H
L
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT88L70AC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:3 Volt Integrated DTMF Receiver |
| MT88L70AE | 制造商:Microsemi Corporation 功能描述: |
| MT88L70AE1 | 制造商:Microsemi Corporation 功能描述:DTMF RX 3.58MHZ CMOS 3V 18PDIP - Rail/Tube |
| MT88L70AN | 制造商:Microsemi Corporation 功能描述: |
| MT88L70AN1 | 制造商:Microsemi Corporation 功能描述:DTMF RX 3.58MHZ CMOS 3V 20SSOP - Rail/Tube 制造商:Microsemi Corporation 功能描述:IC 3V INTEGRATED DTMF RCVR |
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