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參數(shù)資料
| 型號(hào)： | MT8888CN1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 信令電路 |
| 英文描述： | ER 5C 5#16S PIN RECP WALL |
| 中文描述： | TELECOM, DTMF SIGNALING CIRCUIT, PDSO24 |
| 封裝： | 5.30 MM, LEAD FREE, MO-150AG, SSOP-24 |
| 文件頁數(shù)： | 20/25頁 |
| 文件大?。?/td> | 536K |
| 代理商： | MT8888CN1 |
MT8888C
Data Sheet
20
Zarlink Semiconductor Inc.
Timing is over recommended temperature & power supply voltages.
Typical figures are at 25
°
C and for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics
-
Voltages are with respect to ground (V
SS
), unless otherwise stated.
Characteristics
Sym.
Min.
Typ.
Max.
Units
Conditions
1
T
O
N
E
I
N
Tone present detect time
t
DP
t
DA
t
PStb3
t
PStRX
3
11
14
ms
Note 11
2
Tone absent detect time
0.5
4
8.5
ms
μ
s
μ
s
Note 11
3
Delay St to b3
13
See Figure 7
4
Delay St to RX
0
-RX
3
8
See Figure 7
5
T
O
N
E
O
U
T
Tone burst duration
t
BST
t
PS
t
BSTE
t
PSE
V
HOUT
V
LOUT
dB
P
THD
50
52
ms
DTMF mode
6
Tone pause duration
50
52
ms
DTMF mode
7
Tone burst duration (extended)
100
104
ms
Call Progress mode
8
Tone pause duration (extended)
100
104
ms
Call Progress mode
R
L
=10k
R
L
=10k
R
L
=10k
25 kHz Bandwidth
R
L
=10k
f
C
=3.579545 MHz
9
High group output level
-6.1
-2.1
dBm
10
Low group output level
-8.1
-4.1
dBm
11
Pre-emphasis
0
2
3
dB
12
Output distortion (Single Tone)
-35
dB
13
14
Frequency deviation
f
D
R
LT
f
C
t
CLRF
DC
CL
C
LO
±
0.7
±
1.5
%
k
15
Output load resistance
10
50
16
X
T
A
L
Crystal/clock frequency
3.5759
3.5795
3.5831
MHz
17
Clock input rise and fall time
110
ns
Ext. clock
18
Clock input duty cycle
40
50
60
%
Ext. clock
19
Capacitive load (OSC2)
30
pF
AC Electrical Characteristics
- MPU Interface -
Voltages are with respect to ground (V
SS
), unless otherwise stated.
Characteristics
Sym.
Min.
Typ.
Max.
Units
Conditions
1
RD/WR clock frequency
f
CYC
t
CYC
4.0
MHz
Figure 18
2
RD/WR cycle period
250
ns
Figure 18
3
RD/WR rise and fall time
t
R,
t
F
t
AS
t
AH
t
DHR
t
DDR
t
PWL
t
PWH
t
DSW
t
DHW
C
IN
20
ns
Figure 18
4
Address setup time
23
ns
Figures 19 & 20
5
Address hold time
26
ns
Figures 19 & 20
6
Data hold time (read)
22
ns
Figures 19 & 20
7
RD to valid data delay (read)
100
ns
Figures 19 & 20
8
RD, WR pulse width low
150
ns
Figures 18, 19 & 20
9
RD, WR pulse width high
100
ns
Figures 18, 19 & 20
10
Data setup time (write)
45
ns
Figures 19 & 20
11
Data hold time (write)
10
ns
Figures 19 & 20
12
Input Capacitance (data bus)
5
pF
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