參數(shù)資料
型號: MT8841AN
廠商: Mitel Networks Corporation
英文描述: CMOS Calling Number Identification Circuit
中文描述: 主叫號碼識別的CMOS電路
文件頁數(shù): 8/10頁
文件大?。?/td> 101K
代理商: MT8841AN
MT8841
5-18
AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25°C and are for design aid only, not guaranteed and not subject to production testing.
*Notes:
1.
dBm=decibels above or below a reference power of 1mW into 600
.
2.
Using unity gain test circuit shown in Figure 6.
3.
Mark and Space frequencies have the same amplitude.
4.
Band limited random noise (200-3200Hz).
5.
Referenced to the minimum input detection level.
6.
FSK input data at 1200 ±12 baud.
7.
OSC1 at 3.579545 MHz ±0.2%.
8.
10k to V
SS
, 50pF to V
SS.
9.
10k to V
, 50pF to V
.
10.
Function of signal condition.
11.
The device will stop functioning within this time, but more time may be required to reach I
.
12.
For a repeating mark space sequence, the data stream will typically have equal 1 and 0 bit durations.
Figure 7 - DATA and DCLK Output Timing
Figure 8 - DR Output Timing
AC Electrical Characteristics
- Timing
Characteristics
Sym
Min
Typ
Max
Units
Notes*
1
PWDN
OSC1
Power-up time
t
PU
t
PD
t
IAL
t
IAH
35
50
ms
2
Power-down time
100
1000
μs
11
3
CD
Input FSK to CD
low delay
25
ms
4
Input FSK to CD
high delay
8
ms
5
Hysteresis
8
ms
6
DATA
Rate
1188
1200
1212
bps
6,12
7
Input FSK to DATA delay
t
IDD
t
R
t
F
t
DCD
t
CDD
1
5
ms
8
DATA
DCLK
Rise time
200
ns
8
9
Fall time
200
ns
8
10
DATA to DCLK delay
6
416
μs
6, 7, 10
11
DCLK to DATA delay
6
416
μs
6, 7, 10
12
DCLK
Frequency
1200
1202.8
1205
Hz
7
13
High time
t
CH
t
CL
t
CRD
415
416
417
μs
7
14
Low time
415
416
417
μs
7
15
DCLK
DR
DCLK to DR delay
415
416
417
μs
7
16
DR
Rise time
t
RR
t
FF
t
RL
10
μs
9
17
Fall time
200
ns
9
18
Low time
415
416
417
μs
7
DATA
DCLK
t
R
t
DCD
t
CDD
t
R
t
F
t
CL
t
CH
t
F
t
FF
t
RR
t
RL
DR
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