參數(shù)資料
型號： MT80C51C-12D
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44
封裝： 1 MM HEIGHT, QFP-44
文件頁數(shù)： 97/170頁
文件大?。?/td> 4133K
代理商： MT80C51C-12D
32
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
8.4
Register Description
8.4.1
WDTCSR – Watchdog Timer Control and Status Register
Bit 7 – WDIF: Watchdog Timer Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt.
WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is
cleared by writing a logic one to the flag. When the WDIE is set, the Watchdog Time-out Interrupt is requested.
Bit 6 – WDIE: Watchdog Timer Interrupt Enable
When this bit is written to one, the Watchdog interrupt request is enabled. If WDE is cleared in combination with
this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding interrupt is requested if time-out in the
Watchdog Timer occurs.
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in the Watchdog
Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hard-
ware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog Timer security while
using the interrupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each interrupt. This
should however not be done within the interrupt service routine itself, as this might compromise the safety-function
of the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a System Reset will
be applied.
Note:
1. WDTON configuration bit set to “0“ means programmed and “1“ means unprogrammed.
Bit 4 – Res: Reserved Bit
This bit is reserved and will always read zero.
Bit 3 – WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in RSTFLR. This means that WDE is always set when WDRF is set. To clear WDE,
WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe
start-up after the failure.
Bit
765
4321
0
WDIF
WDIE
WDP3
–
WDE
WDP2
WDP1
WDP0
WDTCSR
Read/Write
R/W
R
R/W
Initial Value
0
X
0
Table 8-2.
Watchdog Timer Configuration
WDTON(1)
WDE
WDIE
Mode
Action on Time-out
1
0
Stopped
None
1
0
1
Interrupt Mode
Interrupt
1
0
System Reset Mode
Reset
11
1
Interrupt and System
Reset Mode
Interrupt, then go to
System Reset Mode
0
x
System Reset Mode
Reset
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