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參數(shù)資料
| 型號(hào)： | MT80C51-36D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 1 MM HEIGHT, QFP-44 |
| 文件頁(yè)數(shù)： | 124/170頁(yè) |
| 文件大?。?/td> | 4133K |
| 代理商： | MT80C51-36D |
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57
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
Figure 11-5.
Input Capture Unit Block Diagram
When a change of the logic level (an event) occurs on the Input Capture pin (ICP0), alternatively on the Analog
Comparator output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered.
When a capture is triggered, the 16-bit value of the counter (TCNT0) is written to the Input Capture Register
(ICR0). The Input Capture Flag (ICF0) is set at the same system clock as the TCNT0 value is copied into ICR0
Register. If enabled (ICIE0 = 1), the Input Capture Flag generates an Input Capture interrupt. The ICF0 flag is auto-
matically cleared when the interrupt is executed. Alternatively the ICF0 flag can be cleared by software by writing a
logical one to its I/O bit location.
Reading the 16-bit value in the Input Capture Register (ICR0) is done by first reading the low byte (ICR0L) and
then the high byte (ICR0H). When the low byte is read the high byte is copied into the high byte temporary register
(TEMP). When the CPU reads the ICR0H I/O location it will access the TEMP Register.
The ICR0 Register can only be written when using a Waveform Generation mode that utilizes the ICR0 Register for
defining the counter’s TOP value. In these cases the Waveform Generation mode (WGM03:0) bits must be set
before the TOP value can be written to the ICR0 Register. When writing the ICR0 Register the high byte must be
written to the ICR0H I/O location before the low byte is written to ICR0L.
For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 70.
11.5.1
Input Capture Trigger Source
The main trigger source for the Input Capture unit is the Input Capture pin (ICP0). Timer/Counter0 can alternatively
use the Analog Comparator output as trigger source for the Input Capture unit. The Analog Comparator is selected
as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in “ACSR – Analog Comparator Con-
trol and Status Register”. Be aware that changing trigger source can trigger a capture. The Input Capture Flag
must therefore be cleared after the change.
Both the Input Capture pin (ICP0) and the Analog Comparator output (ACO) inputs are sampled using the same
technique as for the T0 pin (Figure 11-3 on page 55). The edge detector is also identical. However, when the noise
canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system
ICFn (Int.Req.)
Analog
Comparator
WRITE
ICRn (16-bit Register)
ICRnH (8-bit)
Noise
Canceler
ICPn
Edge
Detector
TEMP (8-bit)
DATA BUS (8-bit)
ICRnL (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit)
TCNTnL (8-bit)
ACIC*
ICNC
ICES
ACO*
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